open-source-silicon.dev

Hello, I am working on interfacing a 3.3V standard cells with 5.0V IO pads using level-shifts inside OpenLane. What are the settings that I need to ensure that the level-shift cells are used in this fashion? Are there any environment variables similar to `set ::env(FILL_CELL) "$::env(STD_CELL_LIBRARY)__fill_*"` that OpenLane uses to check for level-shift cells as well?

Thanks

afaik no multivoltage support in OpenLane

<@U01AS2SDR7S> curious if it would work to simply add them to the netlist, and let openroad autoroute them?

do you care about the routing happening a certain way?

I would need the router to recognize the two different power rails in order to make sure the functionality is retained for the interfacing with the IO pads. I have attempted to leave the level-shift cells in the lib, lef, spice, and magic files in the Caravel PDK and the result layout, post-routing, seemed to ignore the split power rail used for the higher voltage and the normal VDD found in the rest of the design.  As far as the placement goes, the placement seemed fine with exception to the spots in the layout where the logic required a buffer cell. In those cases, the placement used the level-shift cells in place of the buffer cells.

<@U01AS2SDR7S> I wonder if it would make sense to nest a pad ring in your own user project area, and then drop your project macro inside of that?

Another thing I can think of, is routing the power signal explicitly in and out of your shifter at the netlist level? There seems to be an option for that in caravel:  <https://github.com/efabless/caravel_user_project/blob/gf180mcu/verilog/rtl/user_proj_example.v#L41-L44>

<@U016EM8L91B> said about this:
```The I/O library is characterized for use at 3.3V (albeit a lot slower than at 5V), so in principle you can assume 3.3V throughout, although you will need to make sure that you don't power the chip up to 5V.```

would the same reason also apply for 1.8V?

<@U02Q5NCBMC5>:  To some extent, yes.  However, some of the external components on the existing development board like the SPI flash will probably cut out below around 2.5V, so you would need to design a new development board around 1.8V operation (and I don't think there's an FTDI part that runs at that low voltage, so it's going to be a lot more work than finding equivalent parts to swap in). (Side note:  We will presumably ship GF180 parts with a board that has components running at 5V, so if you're designing even for 3.3V operation, you will want to use the existing board we made for sky130, with the 1.8V domains bypassing the LDO and shorted to the 3.3V domain.)  When designing for 3.3V or 1.8V operation, you will definitely want to use the liberty files for the I/O that are specific to operation at those supply voltages.

<@U01AS2SDR7S>:  You'll probably need to do something like we did on Caravel in Sky130, which is to create a macro for the immediate circuitry around the level shifters.  If you look at the layout for `mgmt_protect` in Caravel, there are three small macros inside the cell;  these are all level shifters or cells operating in a different voltage domain.  There's a similar macro inside `gpio_control_block`.  There's also an isolated cell coming in from the reset pin, but that's away from other circuitry and was just routed on the top level like any other macro.