hi All , can anybody let me know the details of on chip SRAM ie there interacting with the pico32 ? Are the SRAMs soldered seperate OR on same die as that of the processor ? What size and cache configuration ? Can the SRAM be treated as a cache or a register file ? Thanks in advance.

Which MPW are you talking about? We used the PicoRV32 only for MPW-one, then switched to a VexRISC. All the chips so far have a combination of register-based memory and SRAM. The PicoRV32 has no cache, and the VexRISC has a ridiculously small cache that is basically useless. Pins are limited, so there is no reasonable way to use an off-chip SRAM. This SRAM is not available to the user project, only to the management SoC. If you have a user project that needs SRAM, you should just add an SRAM module to your user project.

@Tim Edwards - thanks. Then it should be the vexRISC. it contains a 1kB of memory ? When you say its accesssible to management SoC - you mean can be used only for running applications using vexRISC ? Also this SRAM is both instruction and datacache ?

I'd have to look at the code implementing it, but I think that the instruction cache is registered, not part of the SRAM.

@Tim Edwards , is the code available to be looked at ?

Well, sure, it's all open source, although being done with LiteX, it's mostly written in Python. It's all in https://github.com/efabless/caravel_mgmt_soc_litex.

@Tim Edwards , i see two RAMS RAM256 RAM256( .A0(dff_bus_adr[7:0]), .CLK(sys_clk), .Di0(dff_di), .EN0(dff_en), .WE0(dff_we), .Do0(dff_do) ); RAM128 RAM128( .A0(dff2_bus_adr[6:0]), .CLK(sys_clk), .Di0(dff2_di), .EN0(dff2_en), .WE0(dff2_we), .Do0(dff2_do) ); the busses seems shared ? Which one is the data and which one is the instruction mem ? Any idea ?

I am not familiar with the VexRISC (contact the openlane team if you want more explanation), but I know that both RAMs are for data; they do not overlap but the enable line for each one corresponds to the decoding of higher memory address bits. Instruction cache (which is about 8 words or so) is all registered (synthesized).