Hi, I wanted to do a mixed-signal simulation. I have two amplifiers and a 15-bit shift register (dlrtn_1). How can I simulate this type of design? Moreover, the Shift Register doesn't have VDD and VSS. How can I use it in analog design for simulation? Thanks.

VDD and GND are not visible as symbol pins but if you click on it a d do a 'q' you see attributes for supply as well as substrate connections. Set these to your supply node names.

I appreciate your help. Please tell me what VNB and VPB are.

If you have very few (10 ... 50) logic standard cells you can simulate everything at the transistor level. Otherwise check out @Tim Edwards

spi2spice.py

(from qflow) script that converts a netlist of standard cells into accelerated Xspice LUT based logic elements. Xschem has such an example (sky130_tests/test_stdcells.sch) where a block containing standard cells is simulated at transistor level together with the same block converted by spi2xspice.py to Xspice logic primitives. Xspice simulation si event based and much faster.

I could never solve a problem with a mixed signal circuit, I always had problems with the pins, I used that circuit as a reference by changing the content of the boxes but it didn't work

For mixed signal LVS with verilog subcks, I had problems getting the pins in symbols for verilog subckts in the correct order. I found that if I arrange the pins in the xschem

*.sym

text file to be in the same order as the verilog ports, LVS would pass.

I can’t to simulate that with xspice

Hi Juan, What was your circuit that you wanted to simulate?

first a simple one to be able to experiment with a big one, an inverter but that didn't even work for me, I always had pin errors

@Mitch Bailey you can change the pin order by descending into the symbol, pressing'q' and copying the 'format' attribute, then go up and do 'q' on the symbol placement, paste the 'format' attribute into the instance attributes and change the pin order. This will be effective for that specific instance. The pin ordering is set such that xschem netlist of std cells matches the standard cell spice netlists extracted from magic and contained in file sky130_fd_sc_hd.spice. If verilog format has a different ordering a different netlisting rule must be used. Another possibility is to add another

format_v="......"

attribute to all standard cell symbols that defines the netlist rule for verilog. If you give the command

xschem set format format_v

spice netlist will use

format_v

as netlist rule for all symbols that have a definition for it or revert to default '`format`' if not defined.

@Stefan Schippers Thanks for the explanation. The discrepancy that I was seeing was not with the standard cells, but with logic hard macros in analog circuits.

@Mitch Bailey I understand, however in case of such discrepancies port order can be customized using above methods. Unfortunately port order mismatch between different cellviews/netlist formats is another constant of the universe. I have seen this happening in all pdks i have workerd on. The problem is mostly with spice netlists because these use positional mapping of ports, while verilog/VHDL use named port association so order doesn't matter.