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<@U016HSAA3RQ> <@U016EM8L91B> We have started IO c...
# mpw-2-silicon
p
@jeffdi @Tim Edwards We have started IO config test on our board, but we fail at the beginning test, when processing "flashing caravel" it says Winbond SRAM not found. Any idea on how to approach this?
m
I found the makefile to not be reliable and consistently got this problem too
this is what eventually worked for me:
make F746ZG # copy fails make copy2 make repl then in the repl type: import io_config io_config.run()
it seems the firmware gets corrupted very easily so I found I had to basically reflash it and copy the firmware every time I run the IO test
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p
Ohh alright thanks, i will try it out.
m
let me know how it goes
p
Actually, I am not able run it. The config_io_o.hex file has some problem when passing it to the board environment, we have tried to regenerate the hex file using the config_io_o.c and parse it to the board, but it is throwing a fail.txt in the board environment with this message "The hex file offset load address is not correct".
a
@Matt Venn I am facing the same issue "Winbond SRAM not found" after trying the steps you suggested. I am attaching a screenshot of my terminal for your reference. Thanks
m
looks like you are missing the mpy-cross tools to recompile the firmware
a
Thanks @Matt Venn. I installed the mpy crosstools, I am still getting error. I am attaching the screenshot. I am getting Micropython dirty error possibly because there are some changes in the make file (in firmware_vex/nucleo directory) I had to make. I think the dirty error is separate and should not be causing the Winbond SRAM not found error. Can you confirm. However, to resolve the dirty error I tried many suggestions mentioned in https://forum.micropython.org/viewtopic.php?t=8992 but they did not work.
d
@Ayushman Tripathi Can you try install mpy crosstools with root permission #Step-2 Install stlink sudo pip install mpy-cross sudo apt-get install libusb-1.0-0-dev #Step-2.1: Clone and compile git clone https://github.com/texane/stlink cd stlink/ cmake . make #Step-2.2: Now we copy the built binaries to their place: cd build/Release/bin sudo cp st-* /usr/local/bin cd ../lib sudo cp .so /lib32 #Step-2.3: Copy udev rules: cd ../../.. sudo cp config/udev/rules.d/49-stlinkv* /etc/udev/rules.d/
After mpy crosstools install, I see atleast "make F746ZG" works, but still flow fails as sm-link reboot after the copy command and losses all the copy contents
Copy code
dinesha@lenovo-i3-10100-07IMB05:~/workarea/efabless/test$ make F746ZG 
mpy-cross flash.py
+ mpy-cross flash.py
mpy-cross io_config.py
+ mpy-cross io_config.py
mpy-cross gpio_config_builder.py
+ mpy-cross gpio_config_builder.py
mpy-cross i2c.py
+ mpy-cross i2c.py
mpy-cross nucleo_api.py
+ mpy-cross nucleo_api.py
mpy-cross boot.py
+ mpy-cross boot.py
#st-flash --connect-under-reset --format ihex write F746ZG_firmware.hex
st-flash --reset --format ihex write F746ZG_firmware.hex
+ st-flash --reset --format ihex write F746ZG_firmware.hex
st-flash 1.6.0
2023-01-14T19:53:31 INFO common.c: Loading device parameters....
2023-01-14T19:53:31 INFO common.c: Device connected is: F7 device, id 0x10016449
2023-01-14T19:53:31 INFO common.c: SRAM size: 0x50000 bytes (320 KiB), Flash: 0x100000 bytes (1024 KiB) in pages of 2048 bytes
2023-01-14T19:53:31 INFO common.c: Attempting to write 579808 (0x8d8e0) bytes to stm32 address: 134217728 (0x8000000)
Flash page at addr: 0x08080000 erasedEraseFlash - Sector:0x6 Size:0x40000 
2023-01-14T19:53:38 INFO common.c: Finished erasing 7 pages of 262144 (0x40000) bytes
2023-01-14T19:53:38 INFO common.c: Starting Flash write for F2/F4/L4
2023-01-14T19:53:38 INFO flash_loader.c: Successfully loaded flash loader in sram
enabling 32-bit flash writes
size: 32768
size: 32768
size: 32768
size: 32768
size: 32768
size: 32768
size: 32768
size: 32768
size: 32768
size: 32768
size: 32768
size: 32768
size: 32768
size: 32768
size: 32768
size: 32768
size: 32768
size: 22752
2023-01-14T19:53:46 INFO common.c: Starting verification of write complete
2023-01-14T19:53:51 INFO common.c: Flash written and verified! jolly good!
#sleep 5
sleep 20
+ sleep 20
cp flash.mpy i2c.mpy gpio_config_builder.mpy nucleo_api.mpy io_config.mpy /media/dinesha/NOD_F746ZG/
+ cp flash.mpy i2c.mpy gpio_config_builder.mpy nucleo_api.mpy io_config.mpy /media/dinesha/NOD_F746ZG/
cp config_io_o.hex /media/dinesha/NOD_F746ZG/
+ cp config_io_o.hex /media/dinesha/NOD_F746ZG/
cp main.py /media/dinesha/NOD_F746ZG/
+ cp main.py /media/dinesha/NOD_F746ZG/
ls /media/dinesha/NOD_F746ZG/
+ ls /media/dinesha/NOD_F746ZG/
config_io_o.hex  DETAILS.TXT  FAIL.TXT	flash.mpy  gpio_config_builder.mpy  i2c.mpy  io_config.mpy  main.py  MBED.HTM  nucleo_api.mpy
Copy code
dinesha@lenovo-i3-10100-07IMB05:~/workarea/efabless/test$ make copy2
mpy-cross flash.py
+ mpy-cross flash.py
mpy-cross io_config.py
+ mpy-cross io_config.py
mpy-cross gpio_config_builder.py
+ mpy-cross gpio_config_builder.py
mpy-cross i2c.py
+ mpy-cross i2c.py
mpy-cross nucleo_api.py
+ mpy-cross nucleo_api.py
mpy-cross boot.py
+ mpy-cross boot.py
cp flash.mpy i2c.mpy gpio_config_builder.mpy nucleo_api.mpy io_config.mpy /media/dinesha/NOD_F746ZG/
+ cp flash.mpy i2c.mpy gpio_config_builder.mpy nucleo_api.mpy io_config.mpy /media/dinesha/NOD_F746ZG/
cp config_io_o.hex /media/dinesha/NOD_F746ZG/
+ cp config_io_o.hex /media/dinesha/NOD_F746ZG/
cp main.py /media/dinesha/NOD_F746ZG/
+ cp main.py /media/dinesha/NOD_F746ZG/
ls /media/dinesha/NOD_F746ZG/
+ ls /media/dinesha/NOD_F746ZG/
config_io_o.hex  DETAILS.TXT  FAIL.TXT	flash.mpy  gpio_config_builder.mpy  i2c.mpy  io_config.mpy  main.py  MBED.HTM  nucleo_api.mpy
Copy code
dinesha@lenovo-i3-10100-07IMB05:~/workarea/efabless/test$ make repl
mpremote connect /dev/ttyACM0 repl
+ mpremote connect /dev/ttyACM0 repl
Connected to MicroPython at /dev/ttyACM0
Use Ctrl-] to exit this shell

>>> import io_config
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
ImportError: no module named 'io_config'
>>>
@Praveen raj My FAIL.TXT in my USB folder, Say's file format is wrong "The application file format is unknown and cannot be parsed and/or processed" I tried without --reset command also does not help;
My ST-Flash version is v1.7
Copy code
dinesha@lenovo-i3-10100-07IMB05:~/workarea/tools/source/stlink$ st-flash --version
v1.7.0-235-g6bc70f7
But Run time, it say's Ver1.6
Copy code
dinesha@lenovo-i3-10100-07IMB05:~/workarea/efabless/test$ make F746ZG
mpy-cross flash.py
+ mpy-cross flash.py
mpy-cross io_config.py
+ mpy-cross io_config.py
mpy-cross gpio_config_builder.py
+ mpy-cross gpio_config_builder.py
mpy-cross i2c.py
+ mpy-cross i2c.py
mpy-cross nucleo_api.py
+ mpy-cross nucleo_api.py
mpy-cross boot.py
+ mpy-cross boot.py
#st-flash --connect-under-reset --format ihex write F746ZG_firmware.hex
#st-flash --reset --format ihex write F746ZG_firmware.hex
st-flash --format ihex write F746ZG_firmware.hex
+ st-flash --format ihex write F746ZG_firmware.hex
st-flash 1.6.0
If you see the config_io_o.hex file, it's not standard hex with check-sum. This is verilog specific hex file for directly loading content into memory for fast simulation. If the config_io_o.hex format is the issue, Not sure how it was working for efabless team
👍 1
When i change to hex write out option to ihex format #$(TOOLCHAIN_PATH)$(TOOLCHAIN_PREFIX)-objcopy -O verilog $< $@ $(TOOLCHAIN_PATH)$(TOOLCHAIN_PREFIX)-objcopy -O ihex $< $@ Now USB file folder FAIL.TXT say's The hex file offset load address is not correct.
In verilog hex file generation, using sed command memory pointer offset changed from @10000000 to @00000000, which is not happening when I moved to intel hex format $(SED_CMD) 's/@10/@00/g' $@ $(SED_CMD) '1,/@00/!d' $@
p
Actually when generating the file using objcopy specify the tag "--change-address 0x8000000", i think this is the correct offset address for the hex file. Because this then changes the FAIL.TXT from what you have to "the hex file you dropped isnt compatible with this mode or device". We can confirm this is the right address, as when we write to flash and verify it, we see the stm32 address: 0x8000000.
d
@Praveen raj I feel we are debugging in wrong direction, config_io_o.hex is flash data for caravel not STM processor, it should have started with 0x0000. When i check the io_config,py file, it has ability read .hex with @ format (i.e verilog hex dump file format) and program the caravel flash. ++++++++++++++++++++++++++++++++++++++ def data_flash(test_name, hex_data, first_line=1): new_hex_file = open(f"{test_name}-tmp.hex", "w") new_hex_data = "" hex_out = [] n_bits = hex_data[0] with open(f"{test_name}.hex", mode='r') as f: line = f.readline() line = line.strip() while line != "": if line.startswith("@"): if first_line > 0: first_line = first_line - 1 else: hex_out = [ line.strip() ] break line = f.readline() +++++++++++++++++++++++++++++++++++++++
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I feel caravel flash access is not working and returning worng jedec value. This is resulting in "Winbond SRAM not found" Error Message File: flash,py if jedec[0:1] != bytes.fromhex('ef'): # if jedec[0:1] != bytes.fromhex('e6'): print("Winbond SRAM not found") sys.exit()
p
Hmm, understandable.
We were trying to change the print statement ubder the jedec id if statements to look, that is the issue originally, buf even though changing that didnt reflect on the Error message.
d
I have enabled debug messages, jedec read value 0xff and expected 0xe6. Not Sure Caravel mfg: 0456 and product = 11 ,& project id = 0x00 are correct or not =================================================================== == Beginning IO configuration test. Testing LOW IO chain... == =================================================================== ** IO Configuration Test for config_io_o Started!! * flashing Caravel Caravel data: mfg = 0456 product = 11 project ID = 00000000 Resetting Flash... status = 0xff JEDEC = b'ffffff' Winbond SRAM not found
👍 1
p
This looks great, i doubt the ids are for our respective projects. But i will look into the issue this way, thanks for the explanation.
d
From Caravel design wise (housekeeping.v) , mfgr_id = 0x456 and prod_id = 0x11, which atleast matches, ++++++++++++++++++++++++++++++++++++++ // SPI Identification assign mfgr_id = 12'h456; // Hard-coded assign prod_id = 8'h11; // Hard-coded assign mask_rev = mask_rev_in; // Copy in to out. +++++++++++++++++++++++++++++++++++++++++++++ it means NUCLEO board the caravel SPI connectivity working and caravel responding. Look like caravel to flash access or connectivity issue?
When I masked the Reset command "slave.write([CARAVEL_PASSTHRU, CMD_RESET_CHIP])" . Now atleast JEDEC = ef4016 value looks good, but caravel flashing still fails =================================================================== == Beginning IO configuration test. Testing LOW IO chain... == =================================================================== ** IO Configuration Test for config_io_o Started!! * flashing Caravel Caravel data: mfg = 0456 product = 11 project ID = 00000000 JEDEC = b'ef4016' ++++++++++++++++++++++++++++++++++++++++++++++++++++++ As per WinBond Data Sheet : https://www.winbond.com/resource-files/w25q32jv%20revg%2003272018%20plus.pdf JEDEC = 0xef4016 is corresponding to Winbond Serial Flash (0xeF) + 25Q32JV-IQ/JQ (0x4016). It means caravel able to read the flash JEDEC signature correctly.
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@Praveen raj any update from your end?. All my debug and waveform capture point me to issue at CS# of winbond Flash memory. i.e Win-Bond Flash Memory always see CS# as zero, Due to this only First SPI transaction is successful.
m
Are either if you available 2pm cet tomorrow? We could take a look together
p
@Dinesh A no progress. @Matt Venn sure i can meet.
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