@proppy: So if you said that the lowest output bit is on GPIO[8], then you're not getting output from channels 8, 9, 10, 11, 13, and 15. This seems like purely an output configuration problem. How have you specified your outputs? What was the calibration result for the device?

I'm confused with LA probes, please correct the understanding I have if it is wrong. Caravan template || firmware || Direction la_data_in -> reg_laX_data_in -> (project to CPU) la_data_out -> reg_laX_data -> (CPU to project) reg_laX_oenb -> Output enable -> Turn to 1 if CPU want to write to LA reg_laX_ienb -> Input enable -> Turn to 1 if CPU want to read to LA

I wanted to change the user_clock2 input clock frequency and reduce it from 10 MHz default to say 1MHz. Does anyone know how I can change it ??

Hi, when I did

make run_analog PART=1

, I keep getting this error showing

fail to receive ready signal from firmware

. I looked at the previous thread and know this is the Nucleo board problem. However I couldn't find the solution to that. Does that mean the only thing I can do is to either change the Nucloe board or test the chip without the board?

I am trying to control the logic analyzer pins, to get inputs from the processor. Not sure where I am going wrong, can anyone please give some insights looking at my firmware code?

Hi, I programmed the below code onto the chip and I was able to monitor the GPIO signal toggling every second, which match the

1e7

delayed cycle in the code

(1e7 *1/10MHz = 1 s)

while(1) {

        reg_mprj_datal = 0x00000000;
        reg_mprj_datah = 0x00000000;

        reg_gpio_out = 0x0;

        delay(10000000);

        reg_mprj_datal = 0xffffffff;
        reg_mprj_datah = 0xffffffff;

        reg_gpio_out = 0x1;

        delay(10000000);

	}

If I changed the delay cycle to

1

, the pulse width of the toggling signal is expected to be

1/10MHz = 100 ns

, However, I can't see the correct waveform toggling at 100ns. My sampling rate of the signal analyzer is

100MS/sec

so I think it's enough. I even tried to increase the delay cycle to 10, 100, 1000 and all showing an unexpected low speed square wave. It seems that the delay cycle should be large enough for the chip to "digest" the program or something? I couldn't figure it out whats happening here?

while(1) {

        reg_mprj_datal = 0x00000000;
        reg_mprj_datah = 0x00000000;

        reg_gpio_out = 0x0;

        delay(1);

        reg_mprj_datal = 0xffffffff;
        reg_mprj_datah = 0xffffffff;

        reg_gpio_out = 0x1;

        delay(1);

	}

I have successfully configured my IO and set them to

C_MGMT_OUT

and here is the entire

gpio_test.c

I'm using. The GPIO I am monitoring here is

IO[8], IO[25], IO[32]

.

@Stanley Lin: Please note that the

reg_mprj_datal/h

registers are driven by a state machine in the housekeeping module and are programmed in four passes (one per byte). That means that its maximum rate is going to be something below 1MHz (I forget how many clock cycles are in the state machine; I'd need to look it up). If you try to drive the GPIO faster than that from the management SoC, the behavior will be a much slower pulse, since the housekeeping will hold the wishbone acknowledge until it has finished the write cycle.

The Logic analyzer pins in mpw2 have been holding me back from testing a lot of parts, so, please help me with my current understanding if you have any idea. I am not able to make LA pins to send data from CPU to user project area. Im not sure what Im missing. I need to send data from processor to User project. Like turn on LA_DATA_OUT (reg_laX_data) 20:24 to 1 but I tried all permutations and combinations with the reg_laX_iena nothing works. My current understanding, reg_laX_oenb -> means nothing if we didnt connect it to anything in your design. reg_laX_iena -> turning on this means giving instructions to the CPU to receive data from that pin. And in the firmware reg_la0_data [31:0] corresponds to la_data_out[31:0] in the caravel/caravan layout frame and so on for other bits. So when we want to configure the LA pins to send data from CPU to user project, one should make the reg_laX_iena for that pin to be 0 and make the reg_laX_data for that pin to be 1?

Hi, I want to know when I got the board and chip, how I can program the code on CPU. what tools I need and what steps I need to do?

Hi @proppy If I would like to disable the

xclk

and short it to

TIM3_CH2

, I need to put jumpers on the red spot showing in the second photo right?

set the channel topic: https://docs.google.com/document/d/18-buwBEBkExbpEgMgOU2R6RWLSAjKd-__qa0c85NKsg/edit

set the channel topic: docs index -> https://docs.google.com/document/d/18-buwBEBkExbpEgMgOU2R6RWLSAjKd-__qa0c85NKsg/edit

has anyone checked the DLL ? to get faster internal clocks?

Does anyone know this

Line magic function not found.

error?

Does anyone know how does reg_mprj_xfer works?

Tim had shared an amazing description earlier.

is the wb_clk_i and wb_rst_i is active by default or do we have to activate it for user area?

they are passed straight through , they are global signals that don't need activating

I have been checking the accuracy of the delay function, and from the definition of the function the implementation seems to be using the timer0 in single-shot countdown mode. I wrote this code to toggle the Low GPIO chain at

1ms

void main()
{
     // Management GPIO Configuration
    reg_gpio_mode1 = 1;
    reg_gpio_mode0 = 0;
    reg_gpio_ien = 1;
    reg_gpio_oe = 1;

    // User GPIO Configuration
    set_registers();
    gpio_config_io();

    while (1)
    {
        
            reg_mprj_datal = 0x00000000; // GPIO0 - GPIO31 High
            delay(10000);        // Delay
            reg_mprj_datal = 0xffffffff; // GPIO0 - GPIO31 Low
            delay(10000);        // Delay
        
    }
}

and from observing the output on a logic analyser it seems to be really off. I have attached a screenshot of the same. Seems like an interesting issue and would love to know the reason behind this. I appreciate any insights on the same.Thanks for all the insights and help.

@Ivan Rodriguez did you get anywhere with serial receive?

or anyone else?

Apart from reading data, no, sending data to the IC seems not working. But I didn't have much time lately to play with that

Same here was able to only transmit data over serial. Receive doesn't seem to work. Was able to achieve the correct waveform by bit banging, but since the timer is completely of, the timing is all over the place.

@Tim Edwards Is there a way to do a gate level sim with sky130 in Icarus with sdf annotation? It looks like the stdcells verilog I have is not annotated with timing information, so I see this error: “Omitting $sdf_annotate() since specify blocks are being omitted”. Is there another verilog file available with the specify blocks? Thanks!

@jeffdi @Tim Edwards is there any way to make sure that the design fabricated in mpw-2 shuttle is the correct design which i had submitted. As i have a doubt that may be my design files got change due to the update in my github repository which was used in MPW-4 shuttle program.

are these "default" settings for the project IO config accurate for MPW-2/3? In particular, will something like UART RX or GPIO input work with the default settings after a reset, or do IOs need to be manually configured for the management core to have GPIO-input as well

also, what is the default state of the management GPIO pin (does it default to an output or is it High-Z / output-not-enabled)? I can't find any docs about this

Hi all, We noticed that our design in user project area is not working properly and we would like to understand why this happens. Previously we verified that the design works in RTL and GL simulations on Caravel design, which had been used for MPW-2 submissions at that time. I have two questions regarding this issue: 1. Which Caravel release in GitHub should be used for RTL and GL simulations regarding MPW-2 tape-outs? 2. Our design waits for a flag to be set by the software running on the core. Can we use the housekeeping block to understand that the wishbone interface is operational after reset?