Hi, I want to design 2T SONOS array. Was there any MPW projects that successfully fabricated and characterized SONOS devices? I would like to use such data if it is available. Or is there any bare SONOS chips available, I can do characterization and share this data.

There were a few SONOS projects on MPWs 1 and 2. You would need to look through the efabless catalog of Open MPW projects to find who was responsible for the designs. The process has the major drawback that we received no IP or documentation for the infrastructure of SONOS memories; only the description of the SONOS FET device and how to create a DRC clean layout. I have a SONOS RAM array, under NDA with SkyWater, but it is not part of the open source offering, and it still doesn't come with any useful documentation, so it would have to be fully reverse-engineered. In principle, one just needs the usual SRAM decoders and sense amps for the FET part of the device, and some high-voltage charge pumps for the program and erase cycles. Ensuring that the devices don't get damaged during the programming and erase cycles is the most tricky part. Figuring out a schedule of programming pulses is mostly trial and error.

Ok, Thanks for your reply. I will go through the MPW catalog for that.