Hi everyone! I'm simulating what is the maximum current a via can carry. For that, I created a layout consisting of a resistor where a single via connects port "in" (in metal 5) and one port of the resistor (in metal 4). Theoretically, due to the small area connecting M5 and M4, there should be maximum current that can flow through the resistor. So, creating a testbench consisting of a single voltage source connecting the cell, varying the voltage source and measuring the current should show how the current reaches a point where it gets "saturated". The point is, after creating the layout, making RC parasitic extractions and associating the testbench with the .spice generated in the extraction, when I run the simulation it doesn't show the saturaton effect. Instead, it shows that a 10A current can flow through a single via (which cannot be real). Does someone know why is this happening? Maybe there is some error in the extraction process. But I haven't found it yet. This are the commands I used to generate the extraction: extract do local extract all ext2sim labels on ext2sim extresist tolerance 10 extresist ext2spice lvs ext2spice cthresh 0 ext2spice extresist on ext2spice

I don't think Saturation / EM effects are in the Vias resistance models. I don't even know if vias resistance is extracted. Look at the extracted netlist and see what's inside. Probably ideal resistor for Vias resistance o just nothing.

Via resistance is extracted by magic into the netlist, but only as ideal resistors. Effects such as saturation would have to be implemented with a behavioral resistor model. I'm not aware of any such models being provided to us by SkyWater in the PDK.

Thank you for replying, Stefan and Tim. Would you guys know if there is another way to know or calculate what would be the maximum current that can flow through M5 and M4 based on the number of vias connected between these levels?

@Jhon Pinto this is a good question. There should be a criteria for #of vias vs current or some other resistance/electromigration rule. In general you want to put more parallel viases on supply networks to reduce voltage drops in your circuit. For signal nets the optimal number of viases depends on many factors: • DFM rules (Design For Manifacturability): more parallel viases are a kind of redundancy, if one vias is not etched correctly and has high resistance the other might be ok, so overall you may have a better wafer yield. • Electromigration rules. Even for signal nets if there is high fan-out / loading capacitance and fast transition times this translates to huge current spikes. This might require more viases (and -maybe-wider metal lanes) for reliability. • IR drop rules. If excessive series reistance is caused by viases put more in parallel. I don't know what tools are available to automatically flag weak points in the designs. I did not find max current / DFM / EM rules for viases in the skywater docs. At the very least if you have the one-vias resistance you can simulate the maximum voltage drop there and add more viases if you see excessive drops.

Keep in mind if your current is AC instead of DC, the via can handle a lot more current.

@Stefan Schippers Wouldn't you think that Electromigration is a lot more dominant that IR drop at the time of imposing the maximum current value? I calculated the Imax for a IR drop of 1.8V in a single vias and it resulted in a >1A current for such voltage drop.

@Jhon Pinto: Depends on what you mean by "dominant". IR drop will kill your circuit immediately. Electromigration will kill your circuit over time.

@Tim Edwards When I referred to "dominant", I meant that, regardless of the time factor, a lower current is needed to kill the circuit through Electromigration, compared to killing the circuit through IR drop.

@Jhon Pinto The most limiting effect depends on the context. If you have a 2mm long supply rail, drawn with a very narrow metal line biasing a power hungry circuit, IR drop may kill your circuit well before reaching any EM limit. As you said for a single Vias EM limit becomes the lowest current limit. Do the same calculation for a 2mm long narrow supply line passing through 10 serial vias connections and many transitions to different metal levels and you get the opposite result, At the end for circuit signoff and tape out you should verify both... • Check maximum supply voltage / ground / reference level drops at worst conditions in any part of the circuit to be lower than maximum allowed levels. • Verify ElectroMigration rules for reliability. ... in addition to all other checks (timing and functional verification on layout extracted netlist, mismatch, antenna check, PVT corners, density rules and more).

@Stefan Schippers You're right. For now, the IR drop simulation is covered by R parasitic extraction. Do you know if there is a way to obtain the current density threshold for the metal electromigration? (Like, for example, obtaining 4mA/um² in M4)