I try to design a mixed signal SoC Now i want P amp R analog open-source-silicon.dev #analog-design

I try to design a mixed signal SoC. Now i want P&a...

Filippo

01/04/2023, 12:36 AM

I try to design a mixed signal SoC. Now i want P&R analog ip (PLL) inside my digital caravel project. I made the blackbox and I add it with gds and lef file pointer to config file. When I run the flow I have this error during macro placement, why?

config.json PLL.lef PLL.v wrapped_pll.v

Mitch Bailey

01/04/2023, 1:13 AM

Can you share your

macro.cfg

Manuel M

01/04/2023, 1:44 AM

afair. I saw this error after renaming macro

lef

and

gds

files, as a result of mismatching
gds
file-name and macro-name. I guess a file with the name
PLL_.gds
has been expected EDIT: Nope, doesn't matter

Mitch Bailey

01/04/2023, 2:06 AM

So it’s working now?

👎 1

Filippo

01/04/2023, 8:47 AM

I change the name of gds and lef file in PLL_.gds and PLL_.lef but it doesnt't work

Filippo

01/04/2023, 8:48 AM

This is my macro file. @Mitch Bailey

macro.cfg

Mitch Bailey

01/04/2023, 1:34 PM

Can you push the relevant files to your repo and share it? I’ll see if I can duplicate the problem.

Filippo

01/04/2023, 1:40 PM

This is my working folder: @Mitch Bailey

Mitch Bailey

01/04/2023, 4:24 PM

Don’t know if this is the reason or not but your logs have

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[WARNING ODB-0186] macro PLL_ references unknown site unithddb1

I’m guessing that this is a typo and what you intended was

unitdbdbl

? However, the macro size appears to be bigger than a double height row and since you’re specific placement in

macro.cfg

, maybe the SITE line is not necessary. Your

openlane/wrapper_pll/runs/mixed_sig/logs/synthesis/1-synthesis.log

has

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8.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \wrapped_pll..
Removed 1 unused cells and 1 unused wires.
<suppressed ~2 debug messages>

Maybe your

PLL_

macro is being optimized out here. The

PLL_

instance is connected to inputs, but the only output is an otherwise unconnected wire

clock_out

. Maybe try

assign io_out[0] clout_out;

before

endmodule

Filippo

01/04/2023, 11:06 PM

Okay thank you, I add clock_out to the output and now place the macro correctly. But I have problems during resizer design .... why overlap?

9-resizer.log

Manuel M

01/04/2023, 11:32 PM

The standard cells overlap the macro. I've noticed in your lef files that

CLASS BLOCK

has been changed to

CLASS CORE

inside the zip file. Undo this change,

BLOCK

is the correct one for macros

👍 1

Filippo

01/04/2023, 11:45 PM

Okay thank you, exist an online detailed flow guide to perform mixed-signal IP? I can't find it ..

Mitch Bailey

01/05/2023, 12:02 AM

See https://open-source-silicon.slack.com/archives/C01EX4ATEKF/p1669974836472069

👍 1

Filippo

01/05/2023, 12:13 AM

I have a last error in lvs, how can i correct?

35-wrapped_pll.lef.lvs.log

Mitch Bailey

01/05/2023, 12:24 AM

Is this the output of

flow.tcl

or are you running LVS separately?

Filippo

01/05/2023, 12:24 AM

The output of flow.tcl (STEP 35)

Mitch Bailey

01/05/2023, 12:28 AM

Is there a

openlane/wrapped_pll/runs/mixed_sig/results/final/verilog/gl/wrapped_pll.v

file? Can you post it?

Filippo

01/05/2023, 12:29 AM

Yeah

wrapped_pll.v

Mitch Bailey

01/05/2023, 12:50 AM

Can you also post your most recent

verilog/rtl/wrapped_pll.v

Filippo

01/05/2023, 8:50 AM

wrapped_pll.v

Mitch Bailey

01/05/2023, 10:37 AM

Your synthesized

wrapped_pll

has

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module wrapped_pll (wb_clk_i,
    wb_rst_i,
    vccd1,
    vssd1,
    io_in,
    io_oeb,
    io_out,
    la_data_in,
    la_data_out);
 input wb_clk_i;
 input wb_rst_i;
 input vccd1;
 input vssd1;
 input [37:0] io_in;
 output [37:0] io_oeb;
 output [37:0] io_out;
 input [63:0] la_data_in;
 output [63:0] la_data_out;

while your rtl has

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module wrapped_pll (
    
`ifdef USE_POWER_PINS
    inout vccd1,	// User area 1 1.8V supply
    inout vssd1,	// User area 1 digital ground
`endif

    input wb_clk_i,
    input wb_rst_i,

    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,

    input  [63:0] la_data_in,
    output [63:0] la_data_out,

);

Since the vccd1 and vssd1 signal types and order are different, I’m thinking that something is not matching. Do you want to upload another zip file?

Filippo

01/05/2023, 11:25 AM

I change a little bit the

wrapped_pll

adding a counter that use the output clock of the PLL, but the error during physical design is the same.

Mitch Bailey

01/05/2023, 2:38 PM

Can you try adding

"FP_PDN_MACRO_HOOKS": ["pll1 vccd1 vssd1 VDD GND"],

to your

config.json

file?

Filippo

01/05/2023, 3:11 PM

Yeah, but I think that the correct way is

"FP_PDN_MACRO_HOOKS": ["pll1", "vccd1", "vssd1", "VDD", "GND"],

with comma separated values, right?

Mitch Bailey

01/05/2023, 3:40 PM

I don’t think the individual values are comma separated but I’m not that familiar with the json syntax. It may yield the same result.

Filippo

01/05/2023, 4:05 PM

I try but the problem persist.

Mitch Bailey

01/05/2023, 4:24 PM

The

FP_PDN_MACRO_HOOK

logic does not do much error checking. Did you try both

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"FP_PDN_MACRO_HOOKS": ["pll1 vccd1 vssd1 VDD GND"],

and

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"FP_PDN_MACRO_HOOKS": ["pll1", "vccd1", "vssd1", "VDD", "GND"],

Filippo

01/05/2023, 4:26 PM

Yes I try both and anyone work.

Mitch Bailey

01/05/2023, 4:43 PM

It seems that the gate level powered verilog used for lvs is generated from the synthesized def file. If the powered connections to the PLL macro are missing from the def file, I don’t think they’ll show up in the verilog. Any error messages about power definitions in your logs?

Filippo

01/05/2023, 4:56 PM

This is my run folder after flow.

runs.zip

Mitch Bailey

01/05/2023, 5:25 PM

Your powered netlist is now correct.

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PLL_ pll1 (.VDD(vccd1),
    .GND(vssd1),
    .ENb_VCO(net2),
    .ENb_CP(net3),
    .REF(net1),
    .CLK(\counter.clk ),
    .VCO_IN(wb_clk_i));

However, your macro is not being connected to power. This depends a lot on how you’ve defined your layout. Let me look.

Filippo

01/05/2023, 5:31 PM

This is my magic layout file

PLL_.mag

Mitch Bailey

01/05/2023, 5:44 PM

I looked at the gds. My understanding is that the macros should have a power mesh up to one less than the top metal layer of the layout (metal4 probably). Your macro has multiple VDD and GND wires that aren’t connected on metal1. The metal4 trunks should run vertical so that the metal5 power grid will connect. But you might want to start a new thread because I probably can’t give much more advice.

Filippo

01/05/2023, 6:21 PM

Okay thank you very much

Filippo

01/05/2023, 8:34 PM

@Mitch Bailey If you see this file

mcu/openlane/wrapped_pll/runs/mixed_sig/logs/signoff/35-wrapped_pll.lef.lvs.log

, at row 2143 there are some mismatch why?

Mitch Bailey

01/06/2023, 1:30 AM

I’ve seen these types of mismatches on similar topologically equivalent nets. If the designs are entirely topologically equivalent, then netgen will rematch nets based on port names. Your design has unconnected power in the PLL macro, and thus is not topologically equivalent and netgen has not done rematching. So ignore the mismatches between topologically equivalent nets.

👍 1

Filippo

01/07/2023, 1:45 PM

If I add VDD and GND in VDD_NETS and GND_NETS in config.json file I encountered a new issue.

Not a floating-point value: PIN (line=8917, cell=, file=wrapped_pll.def) in Layout.read

What is?

Filippo

01/07/2023, 1:47 PM

wrapped_pll.def

Mitch Bailey

01/07/2023, 2:08 PM

Sorry, I have no clue. My suggestion is to find a mixed-signal design and see how they solved the problem.

Filippo

01/07/2023, 2:10 PM

Have you any git hub link project suggestion for this purpose?

Mitch Bailey

01/07/2023, 2:18 PM

Anything here help? https://open-source-silicon.slack.com/archives/C016G7Z8GDR/p1628895681037400

👍 1

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