Is it possible to use VHDL description of design instead of Verilog for openlane rtlToGds flow?

If you want to stay within the flow of OpenLane, then no. The provided version of YOSYS is only for Verilog, not VHDL or SystemVerilog. Of course, you can always covert your code using an outside method. I had the same question and decided it was safer to manually rewrite my design into Verilog than attempting to fiddle with the community-debugged tool flow.

Thank you @Wallie Everest, for detailed information.