Mitch Bailey
12/22/2022, 2:01 AMuser_proj_example.
user_proj_example has no text and thus all extracted ports are automatically generated names.
user_project_wrapper has met5-met4 connections at the top layer above the sram power rails, but there is no connecting layer at the user_proj_example layer.
It looks like the sram power rails are not being extracted with connections to the top layer.
Any workarounds?
It seems that cells without text have issues when extracting with magic. Would it be possible to virtually flatten these cells when extracting?
user_project_wrapper met5 ----------------
via4 |
met4 ---
user_proj_example
sram macro pin met4 ----------------Tim Edwards
12/22/2022, 3:09 AMmerge statement in the .ext file that connects down several levels in one merge line. Then ext2spice is supposed to find those intermediate levels and assign them as ports to the intermediate level subcircuit. Whether all that works in all cases is anybody's guess---your example suggests the answer is that it doesn't.
Flattening in place is a new feature but should work for this. Instead of flattening the entire layout, you can just do flatten <instance_name> -inplace, and the instance <instance_name> will be immediately replaced by its flattened contents. I do not have a method to flatten by a single level (or specified number of levels) of hierarchy, though. It works quite well for running LVS on the GF I/O and SRAM. I would expect it to work here, as well.Mitch Bailey
12/22/2022, 4:48 AM