Hi, <@U017X0NM2E7> Iam trying lvs for such a dac c...
# magica
Ahmed Reda
12/21/2022, 1:24 AMHi, @Mitch Bailey Iam trying lvs for such a dac circuit however, the library spice for
sky130_fd_sc_hvl__lsbuflv2hv_1m
Mitch Bailey
12/21/2022, 2:03 AMThis https://github.com/google/skywater-pdk/issues/349
@Tim Edwards I thought this was patched, but maybe I’m thinking of a similar circuit.
@Ahmed Reda it’s a pdk issue.
You can make a temporary fix by copying
sky130_fd_sc_hvl.spicesky130_fd_sc_hvl__lsbuflv2hv_1a_686_151#VGNDa_1606_563#VPWRt
Tim Edwards
12/21/2022, 2:25 AM@Mitch Bailey: Quick edit to your response above: Replace
a_686_151#VGND👍 1
Tim Edwards
12/21/2022, 2:30 AM@Mitch Bailey: Long answer: The invalid SPICE got into the google repository by being generated with an older version of magic, long since fixed in magic, but the error still persists in the generated cells in the PDK source. It probably makes the most sense to write a quick patch script for it. In theory, the original set was also generated from magic, so it might work just to tell open_pdks to generate the SPICE from scratch rather than copying it from the source. But that part of the Makefile is a bit complicated, so it might be simpler to write the patch script and do a simple regsub replacement. Need to figure out how many cells are incorrect in that library. It's not very many, as it can only occur in the double-height cells, of which there are only a handful.
Tim Edwards
12/21/2022, 2:33 AM@Ahmed Reda: The DAC in question (which I designed) has a fixed copy of the netlist for
sky130_fd_sc_hvl__lsbuflv2hv_1Tim Edwards
12/21/2022, 2:42 AM@Mitch Bailey: And yes, you were thinking of another cell, which is the
hv2lvlv2hvTim Edwards
12/21/2022, 3:05 AM@Mitch Bailey: I uncovered another problem when trying to create the corrected netlist. The nets that are connected only by label mess up the port order, so the port order no longer follows the indexes in the .mag or the .ext file. . .
👍 1
Tim Edwards
12/21/2022, 3:19 AM@Mitch Bailey, @Ahmed Reda: open_pdks version 1.0.378 will have the corrected netlist of this cell. But there are probably other cells in that library that remain incorrect.
a
Ahmed Reda
12/21/2022, 2:08 PMThanks @Mitch Bailey @Tim Edwards .I would like to inform that
1-
sky130_fd_sc_hvl.spicesky130_fd_sc_hvl__lsbuflv2hv_1sky130_fd_sc_hvl__lsbuflv2hv_1m
Mitch Bailey
12/21/2022, 2:27 PMYou might have an older version of the schematic that had too many dummy cells. @Tim Edwards I think I pushed a change to the closed source version. Do you know if it made it to the open source version?
t
Tim Edwards
12/21/2022, 2:39 PMI have never been entirely sure which version is where.
Tim Edwards
12/21/2022, 2:41 PMThere is also a version where the low bit is flipped, leading to non-monotonic output from simulation, that kept popping up long after I thought I had fixed it.
m
Mitch Bailey
12/21/2022, 3:52 PM@Ahmed Reda Where’s your repo? I’ll try to create a PR for the changes.
a
Ahmed Reda
12/21/2022, 4:41 PM@Mitch Bailey here you are. The recent version is here after fixing flipping the low bit.
https://github.com/efabless/analog-mixed-signal-blocks/tree/main/blizzard_adc_corrected/dac_3v_8bit
m
Mitch Bailey
12/21/2022, 5:14 PMLooks like that might be a closed repo. Let me see if I can access it with a password.
a
Ahmed Reda
12/21/2022, 5:34 PM@Mitch Bailey ok, can you please try this link
https://gitlab.com/efabless/designs/blizzard/-/tree/adc/macros/dac_3v_8bit
m
Mitch Bailey
12/22/2022, 12:25 AM@Ahmed Reda Are you sure that’s the right spice file? I couldn’t find the
dac_3v_8bita
Ahmed Reda
12/22/2022, 4:27 AMm
Mitch Bailey
12/22/2022, 5:39 AMMaybe try this (I think this is what I used to pass LVS)
a
Ahmed Reda
12/22/2022, 7:04 PM@Mitch Bailey @Tim Edwards.Thanks you for your guidance and help. Device classes dac_3v_8bit and dac_3v_8bit are equivalent. However,
I am wondering about if there is a command to avoid extracting unreal ports to match. Or should i remove it manually
t
Tim Edwards
12/22/2022, 7:51 PM@Ahmed Reda: It's possible that's caused by the version of magic. I think with the most recent versions of magic and the tech file from open_pdks, it should not have issues with the extra pins (they won't be seen as pins). At least when I look at the GDS you posted, I don't see the bit lines showing as ports in the layout.
✅ 1
a
Ahmed Reda
12/22/2022, 9:23 PM@Mitch Bailey can you please check contents of
gds.analog.spice.tclt
Tim Edwards
12/23/2022, 2:09 PMIt should not be necessary to do any flattening on GDS read. This layout was created by magic and should read back into magic without issues.
The line
property "-dac_3v_8bit $dev" delete mult perim pjm
Mitch Bailey
12/23/2022, 2:50 PM@Tim Edwards This looks like a modified version of the script that I use in a shell script to extract gds. Some of the hierarchy has no pin/text (IIRC), so using
flatglob4 Views