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My design is failing at step 22, while doing the I...
# openlane
a
My design is failing at step 22, while doing the IR drop analysis. Can anyone help me ? How to solve this problem ?
v
Log says there are unconnected 
vccd1
net. Can you fix those issue?
file an issue in https://github.com/The-OpenROAD-Project/OpenLane/issues with 
issue_reproducible
generated by flow as testcase
✅ 1
a
I have seen the log file, I have check my .v file where I had define vccd1 and vssd1.
v
can you share your repo link or source rtl file?
a
Copy code
module user_project_wrapper #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,		// User area 5.0V supply
    inout vssd1,		// User area ground
`endif

    // Wishbone Slave ports (WB MI A)
    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,

    // Logic Analyzer Signals
    input  [63:0] la_data_in,
    output [63:0] la_data_out,
    input  [63:0] la_oenb,

    // IOs
    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,

    // Independent clock (on independent integer divider)
    input   user_clock2,

    // User maskable interrupt signals
    output [2:0] user_irq
);
   
    user_proj_asic mprj(
        .wb_clk_i(wb_clk_i),
        .wb_rst_i(wb_rst_i),
        .user_clock2(user_clock2),
        .A_PAD(io_in[0]),
        .B_PAD(io_in[1]),
        .sel(io_in[2]),
        .OUT_1(io_out[3]),
        .OUT_2(io_out[4])
    );


endmodule	// user_project_wrapper


module user_proj_asic #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,		// User area 5.0V supply
    inout vssd1,		// User area ground
`endif

    // Wishbone Slave ports (WB MI A)
    input wb_clk_i,
    input wb_rst_i,
      // IOs
    input   A_PAD,
    input   B_PAD,
    input sel,
    output OUT_1,
    output OUT_2,
 
    // Independent clock (on independent integer divider)
    input   user_clock2

  );
  endmodule
`default_nettype wire
This is my top wrapper, I am hardening my macros with caravel user project wrapper
v
share 
config.json
and you're working for MPW-8 shuttle right?
m
I don't see any power connections here.
Copy code
user_proj_asic mprj(
        .wb_clk_i(wb_clk_i),
        .wb_rst_i(wb_rst_i),
        .user_clock2(user_clock2),
        .A_PAD(io_in[0]),
        .B_PAD(io_in[1]),
        .sel(io_in[2]),
        .OUT_1(io_out[3]),
        .OUT_2(io_out[4])
    );
✅ 1
v
a
@Vijayan Krishnan Yes, I am submitting my project in MPW-8
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{
  "DESIGN_NAME": "user_project_wrapper",
  "VERILOG_FILES": [
    "dir::../../verilog/rtl/defines.v",
    "dir::../../verilog/rtl/user_project_wrapper.v"
  ],
  "CLOCK_PERIOD": 10,
  "CLOCK_PORT": "user_clock2",
  "CLOCK_NET": "mprj.clk",
  "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
  "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
  "VERILOG_FILES_BLACKBOX": [
    "dir::../../verilog/rtl/defines.v",
    "dir::../../verilog/rtl/user_proj_asic.v"
  ],
  "EXTRA_LEFS": "dir::../../lef/user_proj_asic.lef",
  "EXTRA_GDS_FILES": "dir::../../gds/user_proj_asic.gds",
  "FP_PDN_CHECK_NODES": 0,
  "SYNTH_ELABORATE_ONLY": 1,
  "PL_RANDOM_GLB_PLACEMENT": 1,
  "PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
  "PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
  "PL_RESIZER_BUFFER_INPUT_PORTS": 0,
  "FP_PDN_ENABLE_RAILS": 0,
  "DIODE_INSERTION_STRATEGY": 0,
  "RUN_FILL_INSERTION": 0,
  "RUN_TAP_DECAP_INSERTION": 0,
  "FP_PDN_VPITCH": 180,
  "FP_PDN_HPITCH": 180,
  "CLOCK_TREE_SYNTH": 0,
  "FP_PDN_VOFFSET": 5,
  "FP_PDN_HOFFSET": 5,
  "MAGIC_ZEROIZE_ORIGIN": 0,
  "FP_SIZING": "absolute",
  "RUN_CVC": 0,
  "UNIT": "2.4",
  "FP_IO_VEXTEND": "expr::2 * $UNIT",
  "FP_IO_HEXTEND": "expr::2 * $UNIT",
  "FP_IO_VLENGTH": "ref::$UNIT",
  "FP_IO_HLENGTH": "ref::$UNIT",
  "FP_IO_VTHICKNESS_MULT": 4,
  "FP_IO_HTHICKNESS_MULT": 4,
  "FP_PDN_CORE_RING": 1,
  "VDD_NETS": [
    "vccd1",
    "vccd2",
    "vdda1",
    "vdda2"
  ],
  "GND_NETS": [
    "vssd1",
    "vssd2",
    "vssa1",
    "vssa2"
  ],
  "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
  "pdk::sky130*": {
    "RT_MAX_LAYER": "met4",
    "DIE_AREA": "0 0 2920 3520",
    "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
    "scl::sky130_fd_sc_hd": {
      "CLOCK_PERIOD": 10
    },
    "scl::sky130_fd_sc_hdll": {
      "CLOCK_PERIOD": 10
    },
    "scl::sky130_fd_sc_hs": {
      "CLOCK_PERIOD": 8
    },
    "scl::sky130_fd_sc_ls": {
      "CLOCK_PERIOD": 10,
      "SYNTH_MAX_FANOUT": 5
    },
    "scl::sky130_fd_sc_ms": {
      "CLOCK_PERIOD": 10
    }
  }
}
@Vijayan Krishnan Please check my jason file
Copy code
@Mitch Bailey 
THis is not not issue, I did try with this one as well, Look at my final.v and still getting the same issue 
module user_project_wrapper #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,		// User area 5.0V supply
    inout vssd1,		// User area ground
`endif

    // Wishbone Slave ports (WB MI A)
    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,

    // Logic Analyzer Signals
    input  [63:0] la_data_in,
    output [63:0] la_data_out,
    input  [63:0] la_oenb,

    // IOs
    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,

    // Independent clock (on independent integer divider)
    input   user_clock2,

    // User maskable interrupt signals
    output [2:0] user_irq
);
   
    user_proj_asic mprj(
    `ifdef USE_POWER_PINS
    .vccd1(vccd1),		// User area 5.0V supply
    .vssd1(vssd1),		// User area ground
    `endif
    
        .wb_clk_i(wb_clk_i),
        .wb_rst_i(wb_rst_i),
        .user_clock2(user_clock2),
        .A_PAD(io_in[0]),
        .B_PAD(io_in[1]),
        .sel(io_in[2]),
        .OUT_1(io_out[3]),
        .OUT_2(io_out[4])
    );


endmodule	// user_project_wrapper


module user_proj_asic #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,		// User area 5.0V supply
    inout vssd1,		// User area ground
`endif

    // Wishbone Slave ports (WB MI A)
    input wb_clk_i,
    input wb_rst_i,
      // IOs
    input   A_PAD,
    input   B_PAD,
    input sel,
    output OUT_1,
    output OUT_2,
 
    // Independent clock (on independent integer divider)
    input   user_clock2

  );
  endmodule
`default_nettype wire
v
@Ali Sabir Is 
user_proj_asic
already hardened separately or doing directly with 
user_project_wrapper
?
a
user_proj-asic is hardened already
@Vijayan Krishnan I am just connected my macro with caravel board.
v
remove 
module user_proj_asic
and other contents from 
user_project_wrapper.v
a
@Vijayan Krishnan Then, How i will integarted them.
v
update your git repo and share me the link to debug further
user_project_wrapper.v
should contain only top level connection.
Copy code
module user_project_wrapper #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,		// User area 5.0V supply
    inout vssd1,		// User area ground
`endif

    // Wishbone Slave ports (WB MI A)
    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,

    // Logic Analyzer Signals
    input  [63:0] la_data_in,
    output [63:0] la_data_out,
    input  [63:0] la_oenb,

    // IOs
    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,

    // Independent clock (on independent integer divider)
    input   user_clock2,

    // User maskable interrupt signals
    output [2:0] user_irq
);
   
    user_proj_asic mprj(
    `ifdef USE_POWER_PINS
    .vccd1(vccd1),		// User area 5.0V supply
    .vssd1(vssd1),		// User area ground
    `endif
    
        .wb_clk_i(wb_clk_i),
        .wb_rst_i(wb_rst_i),
        .user_clock2(user_clock2),
        .A_PAD(io_in[0]),
        .B_PAD(io_in[1]),
        .sel(io_in[2]),
        .OUT_1(io_out[3]),
        .OUT_2(io_out[4])
    );


endmodule	// user_project_wrapper
Copy code
`default_nettype wire
try above wrapper file and run and let us know
a
Dear @Vijayan Krishnan My design is mul_asic_16*16, I did created top wrapper for my design that is user_proj_asic, Than i have integrated them with top wrapeer
@Vijayan Krishnan Why did you removed the black box defination ?
v
I think its good to study more about the RTL integration. Anyway you've already hardened the macro and included as 
VERILOG_FILE_BLACKBOX
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"VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_asic.v"],
    "EXTRA_LEFS": "dir::../../lef/user_proj_asic.lef",
    "EXTRA_GDS_FILES": "dir::../../gds/user_proj_asic.gds",
So not required to add same module in 
user_project_wrapper.v
. The other way it should be quoted inside (* blackbox *) is acceptable.
a
@Vijayan Krishnan I am facing the same error after running your wrapper
v
can you share your project link from here: https://platform.efabless.com/projects/public
a
right now, I did not submitted in efabless.
Is it possible, I can give you acces of my pc through any desk
Let's find out the problem togather
m
In your config file, you have
Copy code
"FP_PDN_CHECK_NODES": 0,
Can you enable that to see if it detects the error earlier?
a
@Mitch Bailey Let me try
@Mitch Bailey I am getting the same error at step 6 during pdn generation
m
Great! Now we know where the problem is. Can you tell which macro is not being connected, or is it both? (check the vccd1 locations). I bet it’s 
wrapped_tms1x00
. Does your 
wrapped_tms1x00
have vccd1 power straps on metal4? 
wrapped_tms1x00
looks kind of short. It has to intersect with a vccd1 line from the 
user_project_wrapper
. Can you check that it does? If it doesn’t, you may be able to solve the problem by moving the macro up or down.
v
Copy code
// Logic Analyzer Signals
    input  [63:0] la_data_in,
    output [63:0] la_data_out,
    input  [63:0] la_oenb,
It should be 128 bit size for sky130 caravel. Whether you're allowed use this GPIO pins range?
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.A_PAD(io_in[0]),
        .B_PAD(io_in[1]),
        .sel(io_in[2]),
        .OUT_1(io_out[3]),
        .OUT_2(io_out[4])
you've to use choose any one hardening option: https://github.com/efabless/caravel_user_project/blob/mpw-8c/docs/source/index.rst#hardening-options, but your 
user_project_wrapper.v
and 
config.json
not matching as per hardening flow.
a
Where is the conflict ?
I am not using logic analyzer
I am just using GPIO
@Vijayan Krishnan Error is in connection of vccd1 and vssd1.
@vijay @Mitch Bailey Thank for your support, I did solve my problem and successfully clears all my pre checks and tapeout job.
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