Greetings, So I am designing a simple LDO with sky130 technology (I know there are already some designs out there on GitHub but they either actually have some issues or do not meet my design requirements). And I am having some problems with the PSRR performance of the LDO. The first schematic below is my error amp for now which is a simple active load diff pair. The second schematic is the LDO itself. The third schematic is the testbench for LDO. For this design, Vdd is set to 2V and Vreg is set to 1.8V. Assuming I have a Vref of 1.8V, so there is no resistive divider here. I am targeting at this point a minimum load current of 100uA and a maximum load current of 10mA. Now I am trying to do the loop-gain analysis in Ngspice (which is the main issue of many designs out there as their loop stability analysis is problematic). Here I have done three different loop-stability analyses: Ochoa's Z method, Middlebrook's method, and Tian's method. The fourth schematic shows the testbench for Ochoa's Z method, and the fifth schematic shows the testbench for Middlebrook's and Tian's method (same testbench but different way of calculations). Just in case if you are curious of how these methods are done, please see the following: Ochoa's Z method: Middlebrook's and Tian's method: http://education.ingenazure.com/ac-stability-analysis-ngspice/ (It is also theoretically possible of doing big cap/ind method as described here: https://www.eecg.toronto.edu/~johns/ece331/lecture_notes/22_LG_simulation.pdf but there are some convergence issue with big cap/ind values in Ngspice so I did not use this method here) I have to note here that all these methods do not disturb DC biasing point, and are taking the loading effect into account. Anyway, I obtained fairly similar results for these method for the loop-gain Bode plot with a load current of 100uA, which I have only shown the Middlebrook's result in the sixth figure, which I understand that the phase margin is pretty bad (as I have not optimized my design yet). It has a DC gain of about 50dB and an unity-gain frequency of 1MHz. And now here is the problem. It is well-established that the PSRR of LDO, before the unity-gain frequency, is approximately equal to 1/L where L is the loop-gain. This means that I should expect a PSRR of around -50dB at DC and start to deteriorate around the unity-gain frequency (and the output decap starts to kick in at high frequency). But the simulation result of the PSRR is not what I expected, which is shown in the seventh schematic, and I am not very sure what causes this. Any insight to this will be extremely helpful!

It all depends for which solution the OP solution converges for the AC simulation. If it is not converging to a desired operation point, the LDO is not working. Most times it means that the amplifier only AC simulation results are for a high voltage gain operation point, and the full LDO is in another. Try to run an OP simulation and see which voltages appear in the inputs and outputs of each gain stage to see if their transistors are in the linear region instead of saturation.

@Chris can you share the parameters used in the testbench?

W_*, L_*, W_PASS, L_PASS, M_PASS, Rfb, Cfb, Vb M_CL

?

Hi @Stefan Schippers thanks for the replay sorry for the late reply as I was pretty busy recently (always before Christmas). Yes, you are right when I was looking into the operating point of the pass transistors it indeed was not always in the saturation region. And I also found that 1.6 is a good Vref that gives higher PSRR (a fun fact is 1.2V is even better - it pushes some transistors in the EA in subthreshold). Anyway, it seems that when the pass transistor is not in the saturation region, despite the fact that I have a good loop gain, the PSRR will still be bad as for instance in the triode region, the pass transistor will be just similar to a resistor which definitely degrades the PSRR performance. I find with this simple topology it is truly hard to NOT let the pass transistor enter the triode region over a big load current range without something like dynamic voltage biasing. Please correct me on this point if I am wrong. Regarding those transistor parameters, actually, they are spitted out by a machine learning program I wrote, and I did not really have those numbers anymore that were generating the plots I posted in this thread. But I have some new numbers here just for double-checking:

.param W_M1=99.14284700155258 L_M1=1.5923711508512497
.param W_M2=W_M1 L_M2=L_M1
.param W_M3=62.245199754834175 L_M3=0.5186023712158203
.param W_M4=W_M3 L_M4=L_M3
.param W_M5=38.738645903766155 L_M5=0.6302975118160248
.param W_pass=26.433438658714294 L_pass=0.518585592508316 M_pass=191
.param Vb=1.082405149936676
.param Rfb=6116.504415869713 Cfb=9.86191400885582e-12
.param f_Vdd=10k
.param Vdd=2
.param Vref=1.8 Vamp=0.1*Vdd
.param IL=10m
.param M_CL=151

Anyway, I think I get a better idea of what is going on here, and thanks for the input again!

Hello, how can I make a graph of the PSRR and the noise?