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Chip-8 <https://github.com/HALxmont/MixPix.git>

Are the spice schematic netlists for `PD_M1_M2` and `SystemLevel` available?

Hi, under the analog/xschem folder you'll find the schematics

in fact the photodiode does not have the schematic because it is just  compatible with a magic generated single device with metal blocking layers. The magic files for this device are in magic/photodiode

Looks like `SystemLevel` macro VDD/VSS (V1V8/VSS in the schematic) is connected to vdda1/vssa1 in the layout. This is normally a 3.3V power supply. Would you rather use vccd2/vssd2?

`SystemLevel` `Ibias` is extracting as connected to vdda2 (also 3.3V). Haven’t figured out why yet.

Hi <@U017X0NM2E7>, first of all thank you for revising our design. As for your comments: (1)  let me check this, i think it is our mistake. (2) we have decided to provide the Ibias current using one of the power rails, in this case vdda2. As far as I remember it has a jumper on the PCB.

image.png

here goes the connector, as far as I understand we can freely connect the power domains as needed

<@U01GLU3UDRD> I believe it is possible to reconnect the external power supplies to set vdda1 and/or vdda2 to 1.8V.
I’m not sure if you can use vdda2 as an Ibias input where Ibias  &lt; 1.8V.
<@U016EM8L91B> Can you comment?

• `vccd1` is connected to `1.8V` through J3. The trace has to be cut if it is supplied externally
• `vddio` is connected to `3.3V` through J5. The trace has to be cut if it is supplied externally


I've copied this from the caravel_board github, seems to be possible to switch between power domains

As for the Ibias lets wait for Tim's opinion

The `vdda` supplies are not connected to anything except for a voltage clamp.  It's a high voltage clamp (nominally for 3.3V, I suppose), but I've never been sure quite what that means because the I/O is rated for anything from 1.8V to 5.5V, so I would assume that the clamp works reasonably well over the range.  But that's just the ESD protection.  Otherwise, sure, you should be able to use one of the `vdda` pins as a 1.8V supply and another one for a bias current input.

`SystemLevel` pin `V1V8` in the schematic/verilog matches the `VDD` pin in the layout. That led to a port mismatch at the top level, but once that was fixed, the design passed soft, lvs, and cvc checks.