open-source-silicon.dev

Chip-6 <https://github.com/JorgeMarinN/3LFCC_AC3E_Tapeout.git>

What’s the purpose of met1/res in `stack_2um_1_5`? I don’t think that extracts like you expect.

I’ve found that hierarchical extract works best if there are pins defined at every level.
You can look at the extracted netlist and find subckts with ‘#’ in the port names - I suggest adding layout pins or flattening before extraction (no need to flatten the actual cells, just set the files to flatten before reading gds.)
```core
fc_pad
flying_cap
nmos_drain
nmos_source
nmos_waffle_36x36
pmos_drain
pmos_source
pmos_waffle_48x48
power_pad_1_5
power_pad_3_5
power_stage
stack30um_1_5
stack30um_3_5
stack_2um_1_5
stack_2um_3_5
unit_cap```

<@U017X0NM2E7> without any devices, the stack subcell disappeared during layout extraction. Then the precheck said that the hierarchy in the netlist didn't match the hierarchy in the gds (consistency error). We added the resistor to force the existance of the subcell and the error was fixed.

I see. Then for LVS, the stacks are ignorable.