Just got chip_io to "pass" LVS!

Subcircuit summary:
Circuit 1: chip_io                                                                |Circuit 2: chip_io
----------------------------------------------------------------------------------|----------------------------------------------------------------------------------
sky130_ef_io__gpiov2_pad_wrapped (44)                                             |sky130_ef_io__gpiov2_pad_wrapped (44)
sky130_ef_io__vccd_lvc_clamped_pad (1)                                            |sky130_ef_io__vccd_lvc_clamped_pad (1)
sky130_ef_io__vddio_hvc_clamped_pad (2)                                           |sky130_ef_io__vddio_hvc_clamped_pad (2)
sky130_ef_io__vssio_hvc_clamped_pad (2)                                           |sky130_ef_io__vssio_hvc_clamped_pad (2)
sky130_ef_io__vdda_hvc_clamped_pad (4)                                            |sky130_ef_io__vdda_hvc_clamped_pad (4)
sky130_ef_io__vssd_lvc_clamped3_pad (2)                                           |sky130_ef_io__vssd_lvc_clamped3_pad (2)
sky130_ef_io__vssd_lvc_clamped_pad (1)                                            |sky130_ef_io__vssd_lvc_clamped_pad (1)
sky130_ef_io__vccd_lvc_clamped3_pad (2)                                           |sky130_ef_io__vccd_lvc_clamped3_pad (2)
sky130_ef_io__vssa_hvc_clamped_pad (4)                                            |sky130_ef_io__vssa_hvc_clamped_pad (4)
sky130_fd_io__top_xres4v2 (1)                                                     |sky130_fd_io__top_xres4v2 (1)
Number of devices: 63                                                             |Number of devices: 63
Number of nets: 904                                                               |Number of nets: 904
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely with port errors.

Subcircuit pins:
Circuit 1: chip_io                                                                |Circuit 2: chip_io
----------------------------------------------------------------------------------|----------------------------------------------------------------------------------
...
**no match**                                                                      |flash_clk_ieb_core (disconnected)
**no match**                                                                      |flash_csb_ieb_core (disconnected)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Cell pin lists for chip_io and chip_io do not match.

Final result: Circuits match uniquely with port errors.

The following cells had property errors:
 sky130_ef_io__gpiov2_pad_wrapped
 sky130_ef_io__vddio_hvc_clamped_pad
 sky130_ef_io__vssio_hvc_clamped_pad
 sky130_fd_io__top_xres4v2

Just had to change the netlist, layout, rule file, and netgen (lol). Now on to caravel.

The

flash_clk_ieb_core

and

flash_csb_ieb_core

pins need to be cleaned up. They were an error (the details of which I have already forgotten) and I had to keep the pins to make LVS pass but they were unconnected, so I moved them to an unconnected layer where they show up as disconnected pins. That was sufficient to get MPW-2/3/4 taped out, but it needs to be cleaned up properly.