How to fix this

Instance: sky130_fd_sc_hd__conb_1:TIE_ZERO |Instance: TIE_ZERO_zero_                   
  VGND = 1                                 |  VGND = 3                                 
  VNB = 1                                  |  VNB = 3                                  
  VPB = 1                                  |  VPB = 3                                  
  VPWR = 1                                 |  VPWR = 3                                 
  HI = 1                                   |  proxyHI = 1                              
  LO = 1                                   |  LO = 1

tie cells not matching??

Create a "black box" entry for the TIE cell. The problem is that verilog does not require that all pins be specified; if an output pin of a verilog module is unconnected, it can be omitted from the instance. When netgen reads the verilog netlist, if it has not already read a library of standard cell modules, then it will determine the pins from the instances in the verilog netlist. That said, the above is not necessarily an error; netgen should note that there is a pin in the layout that doesn't exist in the schematic, but if both layout and schematic have nothing attached to that pin on any instance, it would not affect the LVS result. I would have to see the rest of the output from netgen to determine where the actual error is being reported.

here is full log

From the log file, the error appears to be that the power supplies are not connected in the layout.

@Tim Edwards Thanks for looking into this. Few more question: 1. How to implement black box for Tie cell ? 2. power supplies are not connect in layout, which mean its an issue from OpenLane flow or input netlist issue. User wrapper netlist https://github.com/merledu/Ghazi_DFT/blob/dft/verilog/rtl/user_project_wrapper.v 3. What _NCxx nets names? What are un-matching net we can ignore

Subcircuit pins:
Circuit 1: azadi_soc_top_caravel           |Circuit 2: azadi_soc_top_caravel           
-------------------------------------------|-------------------------------------------
...              
vssd1                                      |vssd1                                      
vccd1                                      |vccd1                                      
user_clock2                                |(no matching pin)                          
---------------------------------------------------------------------------------------

Your layout has an extra unconnected pin. Is that ok? Also, your top level has 2 instances. Is that what you're expecting?

Subcircuit summary:
Circuit 1: user_project_wrapper            |Circuit 2: user_project_wrapper            
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__conb_1 (1)                |sky130_fd_sc_hd__conb_1 (1)                
azadi_soc_top_caravel (1)                  |azadi_soc_top_caravel (1)                  
Number of devices: 2                       |Number of devices: 2                       
Number of nets: 645 **Mismatch**           |Number of nets: 641 **Mismatch**           
---------------------------------------------------------------------------------------

Is

conb_1

connected to power?

how to power this standard cell?

@Mitch Bailey: From the number of such errors I've seen reported, it seems like the verilog we provide for the user project wrapper is missing the

user_clock2

pin, maybe?

@Vijayan Krishnan Do you want a standard cell in your

user_project_wrapper

? I think there's something in the config file about whether or not to do placement at the top level.

@Mitch Bailey can you please share doc link about placement at top level allowed or not?

Couldn't find it here https://openlane.readthedocs.io/en/latest/configuration/README.html# But the

caravel_user_project/openlane/user_project_wrapper/config.tcl

has

# The following is because there are no std cells in the example wrapper project.
set ::env(SYNTH_TOP_LEVEL) 1

Yes, we can use standard cell along with macro as per this

config.tcl

https://github.com/efabless/caravel_ibex/blob/master/openlane/user_project_wrapper/config.tcl. With this LVS issue resolved and magic drc errors reported. Need to use

GRT_OBS

i think. Still exploring on this.

screen shot? or gds data. please.

@Mitch Bailey sorry for the late response. Here is final gds

Are you still getting the same drc errors at the same coordinates?

Local interconnect spacing < 0.17um (li.3) ---------------------------------------- 1868.165um 1876.785um 1868.320um 1876.870um 1868.335um 1876.700um 1868.490um 1876.785um 1868.165um 1876.700um 1868.320um 1876.870um 1869.110um 1876.785um 1869.265um 1876.870um 1869.110um 1876.700um 1869.265um 1876.870um 1868.940um 1876.700um 1869.095um 1876.785um Getting this Magic DRC error

Looks like it's inside an SRAM module. SRAM modules use different, less strict rules. I believe the precheck substitutes a LEF version of the SRAM modules to avoid the DRC errors. Maybe the #openram people could help.