@Mitch Bailey: I have just been discussing the verilog-to-SPICE conversion with Mehdi yesterday and today. One way to do that from a verilog gate-level netlist is just to use yosys with the

write_spice

command. Apparently if you give it a netlist without power connections it will unhelpfully produce a SPICE netlist without power connections. But you can use qflow's

vlog2Verilog

to convert a verilog netlist without power connections to one with power connections.

Thanks for the tip, Tim. I think I'm to the point where I can start to debug the caravel device level LVS. All the components are passing individually. After that, I may look into using qflow and yosys to get a chip level spice netlist from the source. I'm not sure that that will be easier to debug than the extracted spice from the layout though.

Hi, I could use this but using standar cell of skywater?