While I'm waiting on an mpw-5 sample caravel, I downloaded slot-001 of mpw-4 and am proceeding with full chip device level LVS. This may not be a critical error, but the verilog instantiation of

simple_por

has 2 vss ports

vss3v3

and

vss1v8

.

simple_por por (
    .por_l(por_l),
    .porb_h(porb_h),
    .porb_l(porb_l),
    .vdd1v8(vccd_core),
    .vdd3v3(vddio_core),
    .vss3v3(vssio_core),
    .vss1v8(vssd_core)
  );

While the layout has only one common

vss

port connected to

vssio_core

.

I put an

isosub

layer in it, but it may not be in the mpw-4 repository (I need to check if it's in the current repository or if I just did that in a local branch).

There is an isosub around the whole cell, but there is only one vss input on the layout (vssio_core) to the whole block. The tap for the 1.8V region vss and 3.3V vss come from the same met4.

Point taken. The HVL inverter should probably be replaced by a proper HV-to-LV level shifter from the HVL library. At very least, since the HVL inverter is powered by the 1.8V domain, its ground side should also be in the 1.8V domain. Since the ground domains are only "virtually" separated, it is not a critical error, but it should be fixed. Better, the power-on-reset circuit should be in a deep nwell with the 1.8V and 3.3V ground domains cleanly separated. I'll post an issue on the github tracker.