https://open-source-silicon.dev logo
Join Slack
Powered by
Hi, I have a design here (<https://drive.google.co...
# lvs
j
Hi, I have a design here (https://drive.google.com/file/d/1TM7ZimVb6vp6tEf68iQNb08SRK6_2_KF/view?usp=sharing ). When I run flow.tcl on it, I get a number of LVS errors. I found out that by varying the DIE_AREA, these LVS errors get better (sometimes 0) or worse. Snippet from log: 
la1_data_out[5]                            |la1_data_out[12] **Mismatch**
la1_data_out[6]                            |la1_data_out[11] **Mismatch**
la1_data_out[7]                            |la1_data_out[10] **Mismatch**
la1_data_out[8]                            |la1_data_out[9] **Mismatch**
It seems like permutations of la1_data_out[x] and io_out[x] signals. In the tarball I'm driving these to 0 or z in my attempt to fix things, but functionally I only need 1 gpio and 1 LA.
Oh, one other change I made that seemed to make LVS succeed is go from clock_period 15 to 20
m
I'll take a look.
I tried to run flow.tcl but it didn't work because my environment is probably different from yours. Can you send me the data in the runs/<tag> directory where you get LVS errors?
j
m
I looked at the netlists and they look logically equivalent. The difference is in the number of antenna diodes connected to intermediary nets. The errors are related to
Copy code
Circuit 2 parallel/series network does not match Circuit 1
Circuit 1 instance INSDIODE2_4 network:
  M = 1 
  M = 1
  M = 1
@Tim Edwards I wondering if resolving automorphism by pin name before resolving by property values would make a difference. Parallel reduction of standard cells (i.e, diode, tap, decap) doesn't do any combination of parameters, correct?
t
@Mitch Bailey: No, that's just weird looking. It's like it tried to parallel combine three subcircuits but somehow failed to actually merge them and left them in some weird state of being collected together but not merged.
m
It's three diode standard cells.
m
I'm also seeing this on my own designs now
sometimes it can be fixed just by a slight size increase or clock change.
very strange
t
Size/clock changes can affect parameters of the synthesis that may change the number and placement of antenna diodes. In effect, that's moving the problem around, not solving it. And you'll have no idea if a change will make the problem go away, or not, or just pop up somewhere else.
✅ 1
m
so probably best thing is to find something reproducable and open an issue
t
I assume the tarball above is a reproducible result. I just finished work on Caravel validation and can spend some time looking into this now.
@Mitch Bailey: What did you do exactly to reproduce the problem? I ran netgen on 
wrapped_dom_1shares.spice
and 
wrapped_dom_1shares.lef.spice
and it worked fine and I get a match with no errors.
m
It may take me a while to respond...
With the data in the attached tarball, 
netgen -batch source setup_file.lef.lvs
reproduces the error with version 1.5.219
wrapped_dom-lvs.tgz
🙌 1
j
@Mitch Bailey @Tim Edwards is it still useful for me to make a bugreport about this? I had some priorities to catch up on, but am happy to still do so now if it's still relevant.
m
Unfortunately, the latest version of netgen 1.5.233 is broken with respect to implicit pins in verilog when running lef LVS. Once that’s fixed, we can revisit this, I think.
With netgen 1.5.228, I get
Copy code
Subcircuit pins:
Circuit 1: wrapped_dom_1shares             |Circuit 2: wrapped_dom_1shares
-------------------------------------------|-------------------------------------------
...
la1_data_out[8]                            |la1_data_out[9] **Mismatch**
la1_data_out[7]                            |la1_data_out[10] **Mismatch**
la1_data_out[6]                            |la1_data_out[11] **Mismatch**
la1_data_out[5]                            |la1_data_out[12] **Mismatch**
la1_data_out[4]                            |la1_data_out[13] **Mismatch**
la1_data_out[12]                           |la1_data_out[4] **Mismatch**
la1_data_out[11]                           |la1_data_out[5] **Mismatch**
la1_data_out[10]                           |la1_data_out[6] **Mismatch**
la1_data_out[9]                            |la1_data_out[7] **Mismatch**
la1_data_out[13]                           |la1_data_out[8] **Mismatch**
...
Circuits match with 108 symmetries.
Resolving automorphisms by property value.
Circuit 2 parallel/series network does not match Circuit 1
Circuit 1 instance INSDIODE2_4 network:
  M = 1
  M = 1
  M = 1
Circuit 2 parallel/series network does not match Circuit 1
Circuit 1 instance INSDIODE2_4 network:
  M = 1
  M = 1
  M = 1
Circuit 2 parallel/series network does not match Circuit 1
Circuit 1 instance INSDIODE2_7 network:
  M = 1
  M = 1
Circuit 2 parallel/series network does not match Circuit 1
Circuit 1 instance INSDIODE2_7 network:
  M = 1
  M = 1
Resolving automorphisms by pin name.
Netlists match with 14 symmetries.
Circuits match correctly.
Result: Cells failed matching, or top level cell failed pin matching.
When resolving automorphisms by property value, I’m wondering if it considers 
M
?
2 Views
Open in Slack
PreviousNext
Powered by