open-source-silicon.dev

layout.spice.txt

magic_spice.txt

comp.out.txt

Hi , LVS in netgen is failing , but not able to debug the reason. The comp.log doesnt seem to be clear , on which nets there are mismatches. Attached are the spice files and the log.

lvs "../../xschem/VLS_1_Low1v8_High5V.spice VLS_1_Low1v8_High5V" "VLS_g5D10_LV1v8_HV5V.spice VLS_g5D10_LV1v8_HV5V"

<@U016EM8L91B> <@U017X0NM2E7> <@U01819B63HP>

<@U02NNT94BK8>:  Just for context, what are you comparing here?  This looks like layout vs. layout, both extracted from magic.

<@U02NNT94BK8>:  I think you failed to post the right netlists.

In general, though, when you get into a situation where the normal netgen output seems to show everything matching, but it still says that the netlists are unmatched, then run the command `debug on` before the `lvs ...` command.  That produces an output that, while harder to read, gives a detailed account of what's at every terminal connection, so that you can see where the differences are when those differences don't show up in a simple fanout count.

Don't forget the setup file!
```lvs "layout_spice layout_top" "schematic_spice schematic_top" $PDK_ROOT/sky130A/libs.tech/netgen/sky130A_setup.tcl```

<@U017X0NM2E7> Thanks -- -i missed providing the setup file !! == oopsie !!! <@U016EM8L91B>