Hi , LVS issue again. Not able to understand failure reason Command : lvs "layout.spice decoder_D1_g5d10" "xschem.spice decoder_4x2_g5D10_xschem" pdks/sky130B/libs.tech/netgen/sky130B_setup.tcl @Mitch Bailey

Here is your extracted layout

.subckt decoder_D1_g5d10 VDD VSS IN0 IN1 OUT0 OUT1 OUT2 OUT3
Xand2_g5D10_0 VDD OUT0 and2_g5D10_1/IN0 and2_g5D10_2/IN0 VDD VSS VSS and2_g5D10
Xand2_g5D10_1 VDD OUT1 IN0 and2_g5D10_1/IN0 VDD VSS VSS and2_g5D10
Xand2_g5D10_2 VDD OUT2 IN1 and2_g5D10_2/IN0 VDD VSS VSS and2_g5D10
Xand2_g5D10_3 VDD OUT3 IN0 IN1 VDD VSS VSS and2_g5D10
Xinverter_d5g10_W1um_L0p420_0 IN0 and2_g5D10_1/IN0 VDD VDD VSS VSS inverter_d5g10_W1um_L0p420
Xinverter_d5g10_W1um_L0p420_1 IN1 and2_g5D10_2/IN0 VDD VDD VSS VSS inverter_d5g10_W1um_L0p420
.ends

You can see that the inputs to

Xand2_g5D10_1

are

IN0

and its inverted signal

and2_g5D10_1/IN0

!

OUT1

will always be low. You probably want this to be

and2_g5D10_2/IN0

instead. Same with

Xand2_g5D10_2

.

I fixed , but still ?

netgen doesn't do gate permutations. The input to series mosfet must be in the same order. In the xschem version

XM2 OUT IN0 net1 VSS sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=0.420 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM4 net1 IN1 VSS VSS sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=0.420 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'

IN1

is input to the nfet connected to ground while

IN0

is connected to the output. In the layout

IN0

and

IN1

are reversed.

Xsky130_fd_pr__nfet_g5v0d10v5_RU632G_0 sky130_fd_pr__nfet_g5v0d10v5_RU632G_0/a_60_n42#
+ IN0 VSS VSUBS sky130_fd_pr__nfet_g5v0d10v5_RU632G
Xsky130_fd_pr__nfet_g5v0d10v5_RU632G_1 OUT IN1 sky130_fd_pr__nfet_g5v0d10v5_RU632G_0/a_60_n42#
+ VSUBS sky130_fd_pr__nfet_g5v0d10v5_RU632G

@Mitch Bailey , i checked now the nets are aligned -- IN0/1 with IN0/1 ...Still issue....

In your xschem netlist, the nand gate has 2 nfet in series:

IN1

is input to the nfet connected to ground while

IN0

is connected to the output. In the layout, these nfets are reversed:

IN0

is input to the nfet connected to ground while

IN1

is connected to the output. Maybe try drawing a transistor level schematic to see the difference.

I guess, need to startover a bit,, since assumption was terminals can be interchangeable.. Thanks a lot @Mitch Bailey

You can always change the schematic to match the layout.

@Ryan R: It is possible to declare gate inputs to be permutable; you would need to copy the netgen setup file locally and edit it to add statements to allow the permutations. The syntax is

permute pins <valid_cellname> <pin1> <pin2> ...