Does anyone have any more advice on how to hard code the configuration of the IO pins? We don't want to use the RISCV core at all in our chip. So maybe someone can explain more about how this works: https://skywater-pdk.slack.com/archives/C017HPHCMEY/p1654277546098159 ? Where do we copy the user_defines.v file? We can get this to work in simulation by copying the

user_defines.v

file into

caravel/verilog/rtl

in our repo here: https://github.com/cornell-ece5745/ece5745-tapeout ... but how does this work? It seems like we are changing some RTL for the Caravel harness but I thought that was a pre-compiled macro or something that gets combined with our user defined logic? We just want to make sure we really understand this so we don't end up messing up the IO configuration ... we would really rather not have to use firmware on the RISCV core just to configure the IO pins ...

@Christopher Batten Are you able to simulate with local change in user_defines.v ?

I think my student @Aidan McNay got that working?

@Dinesh A Yup! When placed in

caravel/verilog/rtl

, user_defines.v controls the power-up configuration of the GPIO's. To simulate with this, you have to not include the GPIO configuration is the simulation (i.e. cut out all of the code about GPIO_MODE and reg_mprj_xfer in your simulation's .c file). This code overwrites whatever the default configuration is for the GPIO's, so to use the default setup, you can't include it