<@U039DRK4BFY> possibly silly question ... can we ...
# chipignite
c
@Nathan Pier possibly silly question ... can we submit multiple times to see how everything works before the final deadline on Friday?
n
@Christopher Batten Yes it's fine to do test submissions. Please change the "Submitter" status back to "Unconfirmed" for the test submissions, though.
👍 1
c
@Nathan Pier we just did a trial tapeout. I think it passed precheck and tapeout. Can you confirm that everything looks good on your end? We will probably submit an improved version tomorrow, but at least we can be confident we have something that is all checked out for tapeout ... thanks!
n
If it passes the precheck then that's a very good indicator, and if you've completed the other items from the instructions tab and set your submitter status to confirmed then your project should be good for submission.
c
ok! I asked @mshalan in a different private channel but haven't head back yet about one thing that has me concerned. Do we need to do anything special if we are using a regular GPIO as the clock? Do we need to change the
CLK_PORT
and
CLK_NET
at the top-level user_project_wrapper? i.e., do we need to change this: • https://github.com/cornell-ece5745/ece5745-tapeout/blob/main/openlane/user_project_wrapper/config.tcl#L41-L42 We have three macros so maybe it should be this?
Copy code
set ::env(CLOCK_PORT) "io_in\[26\]"
set ::env(CLOCK_NET) "grp_15.clk grp_99.clk grp_17.clk"
what does this even -do- if we are not really doing any clock tree buffering at the top level?
n
Mohamed Shalan is based in Egypt so please give him some time to reply. Thanks for your patience.
c
ok. I think we are just using io_clk[10] and then we list the four clock pins of the four blocks ... to be honest I am not sure if it matters at the top level