Hi All , suppose i have spice level of user_analog_project_wrapper , integrated with my block. Is it possible to run spice level simulation with the processor + peripherals + wishbone bus etc...and monitor outputs at the IOs or internal nets also ? Thanks @Tim Edwards

It is, although it is a rather complicated setup. My preference is to create some trivial behavioral model of the analog part of the circuit, even if it's just to generate a digital pulse on what would be an analog signal output, just so you can catch that in a testbench and make sure it's connected correctly. Simulating an entire system with substantial digital parts in ngspice really requires using the xspice event-driven simulator, which is built into ngspice. If you download my synthesis tool

qflow

, there's a script

spi2xspice.py

that will convert a SPICE subcircuit with digital standard cells into its equivalent xspice form. Then the next problem is generating a stimulus for the whole circuit. There is an obscure branch of the ngspice source code that contains an xspice primitive called

d_hdl

that can be used to get iverilog to run ngspice as a co-simulator, for which you can have a testbench written in verilog, including the emulation of the SPI flash. If your analog system can run without needing to run a program on the processor, then you could test it without co-simulation, by applying simple PWL voltage sources to the power supplies and the reset pin. If you need to simulate running a program on the SPI flash, then you would have to do a co-simulation.

actually , the block is totally analog. wanted to emulate the full system simulation setup with the risc processor in caravel , by programming it , and then control the wishbone bus and/or the LA pins , which would feed the analog block inside the user analog project wrapper...Now im not really sure till what level is possible ? Only RTL based simulation or spice too...