Could anyone suggest a good open source 'system verilog' simulator?

icarus should support some system verilog. Not sure though how many features http://iverilog.icarus.com/

iverilog has pretty marginal support for SV. It depends a lot on just how much system verilog syntax is in the RTL code. Don't expect too much of it. . .

Not always fully SV compliant but Verilator does a good job https://www.veripool.org/verilator/

Thanks