Hi all! I am trying to set up GL simulations (GLSIM) with functional model of SRAMs. I am not sure, of the exact steps, but my naive approach right now is to simply replace verilog source with netlist and run the same functional simulations. However, the GLSIM make command is slightly different from the RTLSIM command:

iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
        -f$(VERILOG_PATH)/includes/includes.gl.caravel \
        -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<

Can someone please explain the use of -DGL flag; the command uses -DSIM for RTLSIM. Also, is it okay to not replace the second line that uses the caravel netlist instead of RTL; that might speed up the simulations. Third, how can I set the SIM and GL flags for this command to take effect. I am running make inside a subdirectory of dv, which defaults it to RTLSIM, but now, I just want make to run the iverilog command corresponding to GLSIM.

@Anuj Dubey: There is another freeware simulator called "cvc" that you can try. I don' t know how it compares to iverilog for performance, though.

Thanks Tim. I'll try giving cvc a shot then. I do remember seeing a RUN_CVC flag in the config.tcl, which is usually commented out. Is that what you're referring to?

No, actually there's a naming conflict between cvc, the verilog simulator, and cvc, the electrical rule checking system from Mitch Bailey.

Aah I see. Okay.