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A nmos transistor can be put inside an insulated p-well, this is done by drawing a nwell ring all around and a deep (buried) nwell implant , this creates a nwell pocket surrounding a p-well. The nmos transistor drawn here has a substrate terminal that can be connected to a different node. For the 5 terminal pfet I really don't know the reason.

magic sometimes does gives unexpected results when extracting layout with no pins.

sky130_fd_pr__pfet_01v8_MGS69Z

is not a pfet. It is a subcircuit containing a pfet. I’d suggest making a copy of your design (if you’re using magic), and flattening the parameterized cells before extracting. If you’re extracting from GDS, just do

gds flatglob sky130_fd_pr__*_[A-Z0-9]*

before gds read.

Hi @Stefan Schippers does that deep nwell come with the transistor or is it something I can draw manually to access the substrate terminal?

I don’t think you’re using the GDS flow.

@Mitch Bailey Is there any difference in circuit information between a flattened cell and a hierarchical one? If I use the same ext2spice (ext2spice cthresh 0), I will get the same capacitance in both cases? Thanks!

@Tim Edwards can you respond to this? IIRC, capacitance is the same whether hierarchical or flat, but resistance is only valid for flattened layouts.

@Connie Duong For sky130 I don't know if nwell ring and buried well has to be drawn manually and then insert the i-pwell nmos devices, or if there is a P-cell for that. On different processes I have worked on the buried well had to be drawn manually.

okay thanks for the update!