I am seeing timing violations while running the latest timing scripts. This happens only for slow corner and on all nom, max and min cases. It appears that mostly same paths are affected (example screenshot attached). Can someone provide guidance on what I need to do to fix this? Thanks a lot

This is caraval RISC core (SOC) to external flash interface violation. Since this violation for Max, I assume caravel team would ignored it as actual caravel clock will be less than 25ns system clock period. Better way is to update caravel clock in sdc.

I took a detailed look at the flagged timing paths with the violations. They are all Max violations of the form: SOC to external flash interface (flash_csb, flash_clk, flash_io0), soc/_30758_ (another ff clocked by clk) and also many timing paths to soc.core.RAM128 and soc.core.RAM256. No other timing violations to user_project_wrapper code is found. This happens for s-ck-max.rpt, s-max.rpt, and s-soc-max.rpt (only these files) in all nom, min and max corners. Can all of these timing path violations be safely IGNORED? If I need to fix all of these paths prior to re-submission, how can I proceed? Urgently need guidance in this area. [Thanks to Dinesh A for replying previously]

@Sam Lim Hi, I think they can be safely ignored since the violations are setup and at the slow corners. As well, they are related to the SoC and the RAM (our side). the slow corner defined for sky130 is an extreme corner (operating voltage

1.6V

, temperature

100C

, HV

3V

) so all the cells have huge delays. Since there are no violations at the typical and fast corner, the

25ns

for caravel clock is left as is. While for the slow corners, we found that the tests pass at

35ns

. Summary: You can safely ignore the violations and the caravel clock period could be increased from

25ns

to fix these violations