I've updated timing scripts and running

make extract-parasitics

got struck more than 2Hrs

2022-11-23 09:37:41,421 | get_macros | INFO | getting pdk macros..
2022-11-23 09:37:41,744 | get_macros | INFO | parsing netlist ./verilog/gl/user_project_wrapper.v ..
Generating LALR tables
WARNING: 183 shift/reduce conflicts

Any help/suggestion?

same situation here, but finally it finished in my case, If you wait it will finish hopefully

Can you send share the netlist?

@Kareem Farid Here is my repo: https://github.com/vijayank88/graphics_controller/tree/main/verilog/gl thanks

Looks like pyverilog is slow for large netlists. I will see what can be done about it

Yes, like you said its slow. seeing some progress and completed. Now running

make create-spef-mapping