Holy cow, these gf180 SRAM are huge compared to the sky130 ones. The pic shows a gf180 256x8 compared to a sky130 256x32 (4x!). Is it the technology or is doing @Matthew Guthaus’s OpenRAM team such a great job ? And rather slow (max frequency >> 5 ns), I remember doing RISC processors in the late 90ies on 180 with TLBs, I$, D$, MMU SRAMs @250MHz (no critics, just technical discussion !).

@Tobias Strauch https://github.com/google/globalfoundries-pdk-ip-gf180mcu_fd_ip_sram/tree/9c411928870ce15226228fa52ddb6ecc0ea4ffbe

@Tobias Strauch We are tearing apart their SRAMs and I'm not quite sure why there is so much overhead. The bitcell is definitely smaller, but the sky130 bitcell isn't that efficient.

This

gf180mcu

is interesting: Lmin for Poly of 0.18um is allowed, but the only available standard cell libs are the ones using the IO transistor with an Lmin of 0.5um. So it looks like the core MOSFET are not part of the open-source PDK.

L=0.6um for the SRAM cells

Note that this is a 5V SRAM. All of our IP for GF180MCU is for 5V operation. Also, this SRAM cell is not as highly optimized as SkyWater (Cypress was a company doing memory chips, after all). It violates some DRC rules but does not have custom OPC hints added to the cell. Andy and I looked at the layout and think that much of the surrounding infrastructure is extremely conservative. Which means that the design is probably very robust, but sure isn't area efficient.