In the GF config.json file there are two places where clock period is specified. Which one takes precedence?

{

"DESIGN_NAME": "user_proj_example",

"DESIGN_IS_CORE": 0,

"VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],

"CLOCK_PERIOD": 10,

"CLOCK_PORT": "wb_clk_i",

"CLOCK_NET": "counter.clk",

...

....

....

"pdk::gf180mcuC": {

"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",

"CLOCK_PERIOD": 24.0,

"FP_CORE_UTIL": 40,

"RT_MAX_LAYER": "Metal4",

"SYNTH_MAX_FANOUT": 4,

"PL_TARGET_DENSITY": 0.45

}

}

from pdk value

pdk::gf180mcuC

so 24ns considered

we should file an issue to cleanup the config, as there are other config value that are duplicated