I have lots of problems with gfmpw-1b. make setup doesn't work. I filed an issue here: https://github.com/efabless/caravel_user_project/issues/333 Even efabless' CI is red for gfmpw-1b (and gfmpw-1c): https://github.com/efabless/caravel_user_project/actions Is this supposed to work?

In gfmpw-1b branch, for user_project_wrapper config.json, the VERILOG_FILES_BLACKBOX needs files from dir:../.../verilog/gl/..... Means, gate level netlist. Is it intended? For sky130 black box files from verilog/rtl/... are required

Observed a new knob "EXTRA_SPEFS" in config.json. what should be included in that? My user_project_wrapper has 4 macros and 1 sram. Should I include min,max,nom spefs of all the macros?

Hi, I want to make a pull request on the PDK, but I'm not sure if it should be made over efabless repo or mabrains development repo. In the pcells, I'm trying to decouple the way that some

draw_*

functions register the GDS on Klayout and put that logic on the PCellDeclarationHelper class. It's not complicated but I don't know which repo I should fork. The motivation is to use functions like

draw_nfet

or

draw_res

directly with gdsfactory, avoiding the

return layout.cell()

and replacing it with

return c

. Registration in klayout should happen after

draw_*

invocation. @Amro Tork

Hi all. I have a question regarding the GF memory macros. I was trying to simulate one of the macros and I noticed that it has a specparam for "Tcyc" among others. And it the clock in simulation is lower than that the memory does not work. My question is that wont using such a block of ram put a upper limit on the speed of clock we can use in the overall design and operation. Is there a way around it if it is indeed a problem.

Also if the memory block to be used is not too large and the area and power overhead can be tolerated could a 2d array of flip flops be used to solve the clock limit issue.

Regards

Is there a schottky diode model for the simulation?

Getting [ERROR PSM-0042] Unable to connect macro Instance to the power grid. Is there any change in the syntax of FP_PDN_HOOKS in config.json

I'm trying to simulate gfmpw-1c. There is no testbench in verilog/dv/. Is there an example how to test the counter in rtl/user_proj_example.v?

Has anyone used any of the

gf180mcu_fd_ip_sram

modules, without modification, in an openlane config file?

caravel_core

uses one here, but it’s in a wrapper. Is that the best way?

I'm facing an issue. SRAM is not able to connect to the power grid when used in user_project_wrapper.v. Will wait for the fix. I have to leave the shuttle

If I write a patch to change caravel to caravan (i.e. remove some of the extra MPRJ I/O and put in the analog pads instead) and have my Makefile run that patch at the appropriate times (like setup) will I be able to use such. I.e. will a human intervene and say no caravel, no OpenMPW?

Can somebody provide a working testbench for gfmpw-1c? The directory verilog/dv is empty and using io_ports, la_test1, la_test2 or wb_port from main doesn't work.

@jeffdi @Mitch Bailey @Tim Edwards Do we have the board breakout for the GF180MPW chips? I can see Skywaters only. Do we have one for GF180MCU?

Hi, The pfet pcell is not generating polygons in my installation of the pdk. I'm attaching a gds with an instance of pfet and nfet, both are registered in the hierarchy but only nfet has visual components. I'm using the commit

e0f692f46654d6c7c99fc70a0c94a080dab53571

patched with this script https://git.1159.cl/Mario1159/osic-stacks/src/branch/main/stacks/chipathon-tools/scripts/patch-open-pdks-gf180.sh The patch is based on the instructions given in Volare is having some troubles, so I'm unable to use another open_pdk commit

This message was deleted.

@Zexi Liu has left the channel

@Tim Edwards @jeffdi are we supporting openframe for gfmpw-1 shuttle ?

@Dinesh A Google shuttles don't do openframes

Hi, I just did a new project setup and tried running the user_project_example however its failing at STEP 9. During the build I see that the openroad process starts consuming all the system memory and my laptop becomes unresponsive, so I think the OS kills the process but I guess this should not be happening.

navaneeth@raptor:riscv_soc$ make user_proj_example
make -C openlane user_proj_example
make[1]: Entering directory '/home/navaneeth/.local/share/Trash/files/riscv_soc/openlane'
# user_proj_example
mkdir -p ./user_proj_example/runs/23_11_18_00_15 
rm -rf ./user_proj_example/runs/user_proj_example
ln -s $(realpath ./user_proj_example/runs/23_11_18_00_15) ./user_proj_example/runs/user_proj_example
docker run -it -u $(id -u $USER):$(id -g $USER) -v $(realpath /home/navaneeth/.local/share/Trash/files/riscv_soc/..):$(realpath /home/navaneeth/.local/share/Trash/files/riscv_soc/..) -v /home/navaneeth/asic/pdk:/home/navaneeth/asic/pdk -v /home/navaneeth/.local/share/Trash/files/riscv_soc/caravel:/home/navaneeth/.local/share/Trash/files/riscv_soc/caravel -v /home/navaneeth/asic/openlane:/openlane -v /home/navaneeth/.local/share/Trash/files/riscv_soc/mgmt_core_wrapper:/home/navaneeth/.local/share/Trash/files/riscv_soc/mgmt_core_wrapper -e PDK_ROOT=/home/navaneeth/asic/pdk -e PDK=gf180mcuC -e MISMATCHES_OK=1 -e CARAVEL_ROOT=/home/navaneeth/.local/share/Trash/files/riscv_soc/caravel -e OPENLANE_RUN_TAG=23_11_18_00_15 -e MCW_ROOT=/home/navaneeth/.local/share/Trash/files/riscv_soc/mgmt_core_wrapper  \
	efabless/openlane:2023.07.19-1 sh -c "flow.tcl -design $(realpath ./user_proj_example) -save_path $(realpath ..) -save -tag 23_11_18_00_15 -overwrite -ignore_mismatches"
OpenLane 30ee1388932eb55a89ad84ee43997bfe3a386421
(with mounted scripts from d054702b2cce04761cc2bc598f6b95c9d8ca7c6c)
All rights reserved. (c) 2020-2022 Efabless Corporation and contributors.
Available under the Apache License, version 2.0. See the LICENSE file for more details.

[INFO]: Using configuration in '../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/config.json'...
[INFO]: PDK Root: /home/navaneeth/asic/pdk
[INFO]: Process Design Kit: gf180mcuC
[INFO]: Standard Cell Library: gf180mcu_fd_sc_mcu7t5v0
[INFO]: Optimization Standard Cell Library: gf180mcu_fd_sc_mcu7t5v0
[WARNING]: SYNTH_MAX_FANOUT is now deprecated; use MAX_FANOUT_CONSTRAINT instead.
[WARNING]: DIODE_INSERTION_STRATEGY is now deprecated; use GRT_REPAIR_ANTENNAS, DIODE_ON_PORTS and RUN_HEURISTIC_DIODE_INSERTION instead.
[INFO]: DIODE_INSERTION_STRATEGY set to 4. Setting RUN_HEURISTIC_DIODE_INSERTION to 1
[INFO]: DIODE_INSERTION_STRATEGY set to 4. Setting DIODE_ON_PORTS to in
[INFO]: Run Directory: /home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15
[INFO]: Saving runtime environment...
[INFO]: Preparing LEF files for the nom corner...
[INFO]: Preparing LEF files for the min corner...
[INFO]: Preparing LEF files for the max corner...
[WARNING]: PDK 'gf180mcuC', SCL 'gf180mcu_fd_sc_mcu7t5v0' will generate errors with instantiated stdcells in the design.
[WARNING]: Either disable QUIT_ON_LINTER_ERRORS or remove the instantiated cells.
[INFO]: Running linter (Verilator) (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/synthesis/linter.log)...
[INFO]: 0 errors found by linter
[WARNING]: 9 warnings found by linter
[STEP 1]
[INFO]: Running Synthesis (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/synthesis/1-synthesis.log)...
[STEP 2]
[INFO]: Running Single-Corner Static Timing Analysis (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/synthesis/2-sta.log)...
[STEP 3]
[INFO]: Running Initial Floorplanning (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/floorplan/3-initial_fp.log)...
[INFO]: Floorplanned with width 2786.56 and height 1724.8.
[STEP 4]
[INFO]: Running IO Placement (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/floorplan/4-place_io.log)...
[STEP 5]
[INFO]: Running Tap/Decap Insertion (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/floorplan/5-tap.log)...
[INFO]: Power planning with power {vccd1} and ground {vssd1}...
[STEP 6]
[INFO]: Generating PDN (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/floorplan/6-pdn.log)...
[STEP 7]
[INFO]: Running Global Placement (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/placement/7-global.log)...
[STEP 8]
[INFO]: Running Single-Corner Static Timing Analysis (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/placement/8-gpl_sta.log)...
[STEP 9]
[INFO]: Running Placement Resizer Design Optimizations (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/placement/9-resizer.log)...
[ERROR]: during executing openroad script /openlane/scripts/openroad/resizer.tcl
[ERROR]: Log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/placement/9-resizer.log
[ERROR]: Last 10 lines:
Using 1e+00 for voltage...
Using 1e-03 for current...
Using 1e-06 for power...
Using 1e-06 for distance...
Reading design constraints file at '/home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/tmp/floorplan/3-initial_fp.sdc'…
[INFO]: Setting RC values...
[INFO RSZ-0027] Inserted 58 input buffers.
[INFO RSZ-0028] Inserted 65 output buffers.
[INFO RSZ-0058] Using max wire length 9189um.
child killed: kill signal

[ERROR]: Creating issue reproducible...
[INFO]: Saving runtime environment...
OpenLane TCL Issue Packager

EFABLESS CORPORATION AND ALL AUTHORS OF THE OPENLANE PROJECT SHALL NOT BE HELD
LIABLE FOR ANY LEAKS THAT MAY OCCUR TO ANY PROPRIETARY DATA AS A RESULT OF USING
THIS SCRIPT. THIS SCRIPT IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND.

BY USING THIS SCRIPT, YOU ACKNOWLEDGE THAT YOU FULLY UNDERSTAND THIS DISCLAIMER
AND ALL IT ENTAILS.

Parsing config file(s)…
Setting up /home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/issue_reproducible…
[WRN] /home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/tmp/placement/9-resizer.sdc was not found, might be a product. Skipping
Done.
[INFO]: Reproducible packaged: Please tarball and upload '../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/issue_reproducible' if you're going to submit an issue.
[ERROR]: Step 9 (placement) failed with error:
-code 1 -level 0 -errorcode NONE -errorinfo {
    while executing
"throw_error"
    (procedure "run_tcl_script" line 219)
    invoked from within
"run_tcl_script -tool openroad -no_consume {*}$args"
    (procedure "run_openroad_script" line 2)
    invoked from within
"run_openroad_script $::env(SCRIPTS_DIR)/openroad/resizer.tcl -indexed_log [index_file $::env(placement_logs)/resizer.log] -save "to=$::env(placement_t..."
    (procedure "run_resizer_design" line 8)
    invoked from within
"run_resizer_design"
    (procedure "run_placement" line 17)
    invoked from within
"run_placement"
    (procedure "run_placement_step" line 8)
    invoked from within
"run_placement_step"} -errorline 1
[INFO]: Saving current set of views in '../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/results/final'...
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at '../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/reports/manufacturability.rpt'.
[INFO]: Created metrics report at '../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/reports/metrics.csv'.
[INFO]: Saving runtime environment...
[ERROR]: Flow failed.
[INFO]: The failure may have been because of the following warnings:
[WARNING]: PDK 'gf180mcuC', SCL 'gf180mcu_fd_sc_mcu7t5v0' will generate errors with instantiated stdcells in the design.
[WARNING]: Either disable QUIT_ON_LINTER_ERRORS or remove the instantiated cells.
[WARNING]: 9 warnings found by linter

make[1]: *** [Makefile:79: user_proj_example] Error 255
make[1]: Leaving directory '/home/navaneeth/.local/share/Trash/files/riscv_soc/openlane'
make: *** [Makefile:123: user_proj_example] Error 2

Any pointers is appreciated.

Hi I am running local pre-checks on my design. I am getting error in xor checks. I am using all the default values for PDN generation and IO pins as per the tag gfmpw-1b and am building the design directly in the wrapper not importing it as a macro. I wanted to ask if reducing the pdn spacing will make a difference in the said issue. Also if I reduce he core area and keep the die area same will it make the xor checks likely to pass. Is changing the core area likely to cause issue in tapeout job?

Hi everyone! I have a bit of a confusion. I have cloned the repository at https://github.com/efabless/caravel-gf180mcu for the upcoming shuttle. The PDK variant that the makefile uses is gf180mcuD, but I've been using the tag gf180mcuC. Can someone clarify which of these tags am I supposed to use?

We're having problems reading gf180 def files with klayout

I am trying to use the SRAM macros in my design, and after a successful run of

make user_project_wrapper

, I am now stuck on the prechecks. Its been 4 hours since the OEB Check started, and it still has yet to complete. I still see CPU activity, but I believe it may be stuck. At best, this is still very annoying.

Hi everyone! I am using this docker image https://github.com/iic-jku/IIC-OSIC-TOOLS in a windows OS. I made a repository using this template https://github.com/efabless/caravel_user_project and cloned it and then started following this tutorial series when I reached physical implementation stage, and tried running the design using make user_proj_timer, I got this permission error. Can someone help me debug it. Thanks! /foss/designs/CaravelProjectPractice/Practice01 > make user_proj_timer make -C openlane user_proj_timer make[1]: Entering directory '/foss/designs/CaravelProjectPractice/Practice01/openlane' # user_proj_timer mkdir -p ./user_proj_timer/runs/23_11_24_07_04 rm -rf ./user_proj_timer/runs/user_proj_timer ln -s $(realpath ./user_proj_timer/runs/23_11_24_07_04) ./user_proj_timer/runs/user_proj_timer docker run -it -u $(id -u $USER):$(id -g $USER) -v $(realpath /foss/designs/CaravelProjectPractice/Practice01/..):$(realpath /foss/designs/CaravelProjectPractice/Practice01/..) -v /foss/pdks:/foss/pdks -v /foss/designs/CaravelProjectPractice/Practice01/caravel:/foss/designs/CaravelProjectPractice/Practice01/caravel -v /foss/tools/openlane:/openlane -v /foss/designs/CaravelProjectPractice/Practice01/mgmt_core_wrapper:/foss/designs/CaravelProjectPractice/Practice01/mgmt_core_wrapper -e PDK_ROOT=/foss/pdks -e PDK=gf180mcuD -e MISMATCHES_OK=1 -e CARAVEL_ROOT=/foss/designs/CaravelProjectPractice/Practice01/caravel -e OPENLANE_RUN_TAG=23_11_24_07_04 -e MCW_ROOT=/foss/designs/CaravelProjectPractice/Practice01/mgmt_core_wrapper \ efabless/openlane:2023.07.19 sh -c "flow.tcl -design $(realpath ./user_proj_timer) -save_path $(realpath ..) -save -tag 23_11_24_07_04 -overwrite -ignore_mismatches" /bin/sh: 1: docker: Permission denied make[1]: * [Makefile79 user_proj_timer] Error 127 make[1]: Leaving directory '/foss/designs/CaravelProjectPractice/Practice01/openlane' make: * [Makefile123 user_proj_timer] Error 2

Hi I am trying to run post layout simulation using the powered verilog generated by openlane. I have included the gf180mcuD cells definition but I am getting error on the power and ground connections of the cells. The issue I think is that the simulator is picking up the functional definition of cells without the power connections defined rather than the one with power connections defined. Is there a way to force the simulator to pick up the correct definitions. @Mitch Bailey @Tim Edwards

Hi, trying to harden the user_proj_example using the gf180mcuD pdk, getting an Error: [ERROR RSZ-0089] Could not find a resistance value for any corner. Cannot evaluate max wire length for buffer. Check over your

set_wire_rc

configuration. Not entirely sure I have everything set up correctly, any assistance would be appreciated. Thanks!

Hello again, now trying to run RTL verification on the user_proj_example, each test is failing. Seems like they're all failing in the same way, here's an example: report_test.<locals>.wrapper_func failed Traceback (most recent call last): File "/usr/local/lib/python3.10/dist-packages/caravel_cocotb/interfaces/common_functions/test_functions.py", line 115, in wrapper_func await func(*args, **kwargs) File "/home/brandonhippe/gf180_test/caravel_user_project/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.py", line 34, in counter_la_clk received_val = int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) ValueError: invalid literal for int() with base 2: '000000xxxxxxxxxx' Seems like each is failing when trying to convert vector with x's to int. Thanks again in advance!

Hi, I try to make an analog circuit(very simple inverter) for OpenMPW GF-1. I have flattened inverter but I get the following error in OEB check. Is there a way to resolve this?

CVC: Setting models ...
ERROR: No model match user_project_wrapper/MX0 M pfet_03v3 ad=1.3p pd=5.3u as=1.3p ps=5.3u w=2u l=0.28u
ERROR: No model match user_project_wrapper/MX1 M nfet_03v3 ad=0.61p pd=3.22u as=0.61p ps=3.22u w=1u l=0.28u
Missing models

nfet_03v3 M
pfet_03v3 M