Hi, I would like to ask several questions regarding evaluation of digital design with SKY130 given that the flow (

!flow.tcl -design

) completed without any error. 1. Does the highest clock frequency usable in the design translate from the

/reports/signoff/25-rcx_sta.max.rpt

timing given that there are no hold time violation? (Ex: data arrival time ~20, so clock freq ~50MHz) 2. How can I find the number of gate used in the design? (Ex: calculate from area report in

/reports/signoff/25-rcx_sta.area.rpt

or calculate from

cell_count

in

/reports/metrics.csv

?) 3. My design violates the default value for

-max_slew -max_cap -max_fanout

. Would this possess any problem? I know that I could set the number higher through the

config.tcl

file but is there any number that MUST not be exceeded for this SKY130 technology? I am sorry for a relatively long questions but I would appreciate any confirmation/clarification.