A friend and I are currently working with the efabless vnc. We have tried both creating netlists fro...
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Nick Grieshop
11/15/2022, 5:35 PMA friend and I are currently working with the efabless vnc. We have tried both creating netlists from xschem for qflow and writing verilog to input into it directly. Both of us get stuck synthesis. The error indicates that there is an issue with the verilog file. I feel like there is something simple we are missing. Any help would be appreciated.
m
Mitch Bailey
11/15/2022, 11:42 PMSo what you are doing is using a GUI to create rtl verilog, and then using that verilog as input to qflow, correct? Could you post your verilog?
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Nick Grieshop
11/16/2022, 5:20 PMYeah. We have been trying to play with analog circuits.
Nick Grieshop
11/16/2022, 5:20 PM// sch_path: /home/user/.xschem/xschem_library/xschem_sky130/sky130_fd_pr/sky.sch
module sky
(
);
wire VDD ;
wire Vin ;
wire GND ;
wire Vout ;
vsource
#(
.value ( 1.8 )
)
Vdd (
.p( VDD ),
.m( GND )
);
vsource
#(
.value ( "pulse(0 )
)
Vin (
.p( Vin ),
.m( GND )
);
nfet3_01v8
#(
.L ( 0.15 ) ,
.W ( 1 ) ,
.body ( GND ) ,
.nf ( 1 ) ,
.mult ( 1 ) ,
.ad ( "'int((nf+1)/2) ) ,
.pd ( "'2*int((nf+1)/2) ) ,
.as ( "'int((nf+2)/2) ) ,
.ps ( "'2*int((nf+2)/2) ) ,
.nrd ( "'0.29 ) ,
.nrs ( "'0.29 ) ,
.sa ( 0 ) ,
.sb ( 0 ) ,
.sd ( 0 ) ,
.model ( nfet_01v8 ) ,
.spiceprefix ( X )
)
M1 (
.D( Vout ),
.G( Vin ),
.S( GND )
);
pfet_01v8
#(
.L ( 0.15 ) ,
.W ( 1 ) ,
.nf ( 1 ) ,
.mult ( 1 ) ,
.ad ( "'int((nf+1)/2) ) ,
.pd ( "'2*int((nf+1)/2) ) ,
.as ( "'int((nf+2)/2) ) ,
.ps ( "'2*int((nf+2)/2) ) ,
.nrd ( "'0.29 ) ,
.nrs ( "'0.29 ) ,
.sa ( 0 ) ,
.sb ( 0 ) ,
.sd ( 0 ) ,
.model ( pfet_01v8 ) ,
.spiceprefix ( X )
)
M2 (
.D( Vout ),
.G( Vin ),
.S( VDD ),
.B( VDD )
);
.lib /usr/local/share/sky130_fd_pr/models/sky130.lib.spice tt
.tran 0.1n 20n
.save all
endmodule
m
Mitch Bailey
11/17/2022, 12:41 AMNot sure where to start. Looks like your schematic has transistors. I think the synthesis tools only work with standard cells. Normally, people start with hand written verilog rtl and synthesis that. However, I haven’t worked with qflow.
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Nick Grieshop
11/21/2022, 1:41 PMFor anyone else looking at this in the future, it is now my understanding that it is best to use magic to layout your design. Use xschem to do the simulation. Then compare both to each other with a layout vs schematic(lvs) tool.
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