#KLayout_lvs_emergency Hi all, We are trying to run the LVS of the overall design including all the individual module (we have 9 individual modules). All of our individual modules are LVS clean (which has been done in magic). We have used KLayout to route our design. ** Is there any scripts available for KLayout to run this final LVS and DRC check on the overall design that would save us some time? TIA

Precheck will run DRC on your full design. For LVS (using GDS), you could try the

mpw-7

branch of https://github.com/d-m-bailey/extra_be_checks.git

export LVS_ROOT=<extra_be_checks repo>
mkdir work
export WORK_DIR=$PWD/work
$LVS_ROOT/run_full_lvs net_top top_verilog_file layout_top top_gds_file

Just add your gl powered verilog to the

$WORK_DIR/verilog_files

file. Let me know if you have problems.