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Hi, Do you know how I can create the schematic of ...
# ieee-sscs-dc-22
s
Hi, Do you know how I can create the schematic of a digital block by its layout or verilog code? Thanks.
m
I just create a symbol with the ports in the same order as verilog for LVS. Do you need it for simulation or LVS?
s
Thank you for your reply. I have the layout of a digital block and want to create its schematic to extract the spice file and do the LVS. Could you please help me to have the schematic of the attached digital block? Thanks.
m
Was this created manually or automatically using openlane?
s
Yeah, it's been created automatically. creating such digital block manually, is somehow impossible.
I mean, How I can use the verilog code to create the gate level schematic? Thanks
m
If you have the powered gate level verilog output from openlane, you can use that to run mixed spice/verilog LVS. You’ll need to create a xschem symbol for the digital block and manually edit the 
*.sym
file so that the symbol pins are in the same order as the verilog ports.
Then create and LVS script that pulls in all the files you need.
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readnet spice $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice 1
readnet verilog verilog/gl/user_proj_example.v 1
lvs {user_analog_project_wrapper.gds.spice user_analog_project_wrapper} {xschem/user_analog_project_wrapper.spice user_analog_project_wrapper} $::env(PDK_ROOT)/sky130A/libs.tech/netgen/sky130A_setup.tcl user_analog_project_wrapper.lvs.report -blackbox -json
s
Hi, I opened Xschem and made a symbol file. I opened the .sym file, but I don't know how I should edit the file to see the pins. I used the Verilog code and the testbench to create the layout automatically. How can I use these codes to automatically generate the digital block's schematic? Thank you.
How can I create a symbol with the ports mentioned in the Verilog file that I wrote? Like what I do in Cadence by importing Verilog to create Cadence Schematic. Thanks.
m
There may be a way to do it automatically, but you can do it manually by creating a schematic in xschem with only the pins that are in the verilog, and then create a symbol from that schematic. See https://open-source-silicon.slack.com/archives/C017P3RAD42/p1659621882999149
Once that is done, you can open the symbol in a text editor and rearrange the ports in the same order as verilog (order in text file is important, not the physical location of the pin on the symbol).
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