Hello Everyone, I am wondering if anyone has any tips to get Openlane to route to pins? I have defined the pin order with a

pin_order.cfg

file and the flow runs with no errors, but when I look at the GDS, it appears that Openlane only routed only about 15% of the pins. I am using a slightly different flow than normal (I’m inputing a structural verilog netlist from xschem and only using elaboration in synthesis) so that might have something to do with the issue? Though I would think this is a problem with the router configuration. I have attached my configuration below. Thanks so much!

{
  "DESIGN_NAME": "controller",
  "VERILOG_FILES": "dir::src/*.v",
  "CLOCK_PORT": null,
  "CLOCK_PERIOD": 10,
  "DESIGN_IS_CORE": false,
  "SYNTH_ELABORATE_ONLY": true,
  "SYNTH_READ_BLACKBOX_LIB": true,
  "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
  "FP_SIZING": "relative",
  "FP_CORE_UTIL": 40,
  "PL_TARGET_DENSITY": 0.45,
  "ROUTING_CORES": 6
}