On the caravan-specific pads, there is no ESD whatsoever, except that there are three clamps for power supplies that can be hooked up (optional, and not connected by default). All the pad connections are metal going straight through from the user project area directly to the pad, with no other connections.

Sorry, I meant caravel, not caravan. I'll have to hook-up some ESD protection for these pins and I'd like to have some starting point

There's not a lot of detailed information available. The

pad_a_esd_0_h

is the pin you connect an analog signal to on the GPIO. There is a 150 ohm resistor between that pin and the pad. The pad has the usual reverse-biased diodes to power and ground rails (VDDIO and VSSIO). You would want additional diodes on the inside connection to that 150 ohm resistor. Is that sufficient information?

Where can I find the 1.8V ESD mosfet layout or pcell generator?

I am not entirely clear about the ESD device models. The layouts appear to be normal MOSFETs with an ESD marker layer around them. I do not think that the ESD marker layer is anything other than a marker layer. There are separate models for these ESD devices, but I don't know how they differ from the corresponding non-ESD models.

Sometimes the ESD MOSFETs (not sure about this specific case) have suppressed silicide on the drain side to create a bit of series resistance. On an analog output (MOSFET drains connected to a pad) you can split your large MOSFET into N smaller ones and give each of them a poly series resistor, and short everything on the pad connection. So the overall series-R is reduced by N, but each smaller MOSFET sees the (larger) R for ESD protection. But generally, on analog output, I would not be too worried about ESD if you have ESD diodes present at the pad. For an input (which means connecting to the MOSFET gate) you need two levels of protection, first, ESD diodes at the pads, then a series-R (around 500Ohm is a good value), and then secondary ESD diodes.

Thanks a lot @Harald Pretl for the detailed information! My worry is that the N+ pwell diode is rated for 5.5V, and I'm not sure if it will protect a thin oxide MOSFET against ESD or antenna effects. I'm trying to emulate the GPIO ESD protection, but even that is confusing. I know the pads are ESD protected, but I'll be using the caravan analog pads for bias, so I'll have to do some ESD protection myself.

@Leonardo Gomes You have a diode from pad to VDD, and a diode from pad to VSS. During normal operation they are reverse biased and thus off. During an ESD event they get forward biased, and thus show a foward diode voltage below VSS or above VDD, depending on the polarity of the ESD pulse. So voltage will be forward diode voltage at ESD current levels (which can be Amperes). During this ESD event the supply clamps keep the VDD close to VSS. What really happens during an ESD event is hard to simulate at Ampere-level current and ns rise times, as every bit of resistance and inductance counts along the path that the ESD current takes.