Hello @Mitch Bailey, I was wondering if perhaps you could help me understand what is wrong here. Netgen says the netlists don’t match, however I may just be blind (or miss understanding), but I don’t see any difference in the net list fragments. Could you take a look? I use a make target to extract all and run all of my lvs:

# run lvs between xschem and magic
.PHONY: netgen_component_lvs
netgen_component_lvs:
ifndef component
	$(error component is not set)
endif
	netgen -batch lvs "./xschem/src/$(component)/$(component).spice $(component)" "./mag/components/$(component).spice $(component)" ./netgen/sky130A_setup.tcl ./netgen/$(component)_comp.out

I have attached the netgen output and the spice files. Thank you so much!

Can you create a gds file from your mag data?

Here you go!

Can I get the

sch

data too?

Maybe your caps are connected with the polarity reversed.

Ah! That’s it. How did you know? I couldn’t gather that from the output….

I split both netlists in half. It’s easier to see the cap ports reversed.

sky130_fd_pr__cap_mim_m3_1/1

vs

sky130_fd_pr__cap_mim_m3_1/2

---------------------------------------------------------------------------------------
Net: w_5020_n4620#                         |Net: net7
  sky130_fd_pr__pfet_01v8/(1|3) = 2        |  sky130_fd_pr__pfet_01v8/(1|3) = 2
  sky130_fd_pr__pfet_01v8/4 = 2            |  sky130_fd_pr__pfet_01v8/4 = 2
  sky130_fd_pr__cap_mim_m3_1/1 = 1         |  sky130_fd_pr__cap_mim_m3_1/2 = 1
                                           |
Net: a_4748_n4940#                         |Net: net8
  sky130_fd_pr__nfet_01v8/(1|3) = 4        |  sky130_fd_pr__nfet_01v8/(1|3) = 4
  sky130_fd_pr__cap_mim_m3_1/2 = 1         |  sky130_fd_pr__cap_mim_m3_1/1 = 1
---------------------------------------------------------------------------------------

Ah…how did you split the netlist?

Manually. Not a trivial process.

Ah, that sounds hard, but something useful to learn. Is there a good resource explaining the process?

Probably would have been easier to create a half layout and half schematic and compare those. I just edited the spice files, separating the devices into 2 groups - those related to

vin_p

and those related to

vin_n

. I used

flatglob

to flatten the pcells in the layout before extracting the gds.

@Mitch Bailey I am sorry for the delay in replying. Thank you so much for your help!

Seemed that even with flatglob, I got the same results as you. Splitting the design in half helped clarify the problem.

Hmm.... interesting. Is there a way to make netgen spit out it's results for all of the nodes? Obviously this would be impractical for large designs, but for small pieces like this with only 40ish nodes, it would be helpful.

I believe there is, but I haven’t used it. @Tim Edwards could you explain how to show detailed connectivity information in netgen?

Add

debug on

to the script before running the

lvs

command. But the output isn't pretty.

@Tim Edwards Thank you. I appreciate the help! I will see what that gives me. I’m trying to learn how to better troubleshoot LVS and in this issue, netgen said it failed, but didn’t print out the node that failed.

@Micah Tseng I think what it did in the full version was to establish correspondence at the capacitor ports and report the rest of the circuit that did not match. In the half version, correspondence was established with the rest of the circuit and the capacitor ports were included in the mismatch. In both cases, netgen reports the nets/devices that it considers not to match.

@Mitch Bailey Huh. That’s interesting. This algorithm rather tickles my brain….I think I need to understand how this algorithm works better.