I have a small issue with lvs when using standard cells. I have the same devices but the netlists do not match. Specifically everything matches except the last two nodes. I see that the devices matched with each node are the correct ones just switched between them. --------------------------------------------------------------------------------------- Net: sky130_fd_sc_hs__dfrtp_4_3/CLK |Net: f4_n sky130_fd_sc_hs__dfrtp_4/CLK = 4 | sky130_fd_pr__pfet_01v8_lvt/2 = 1 | sky130_fd_pr__nfet_01v8_lvt/2 = 1 | sky130_fd_sc_hs__dfrtp_4/8 = 1 | sky130_fd_sc_hs__inv_16/1 = 1 | Net: sky130_fd_sc_hs__inv_16_6/A |Net: clock sky130_fd_pr__nfet_01v8_lvt/2 = 1 | sky130_fd_sc_hs__dfrtp_4/1 = 4 sky130_fd_sc_hs__dfrtp_4/Q = 1 | sky130_fd_sc_hs__inv_16/A = 1 | sky130_fd_pr__pfet_01v8_lvt/2 = 1 | --------------------------------------------------------------------------------------- There are also some device mismatches that seem correct and show a pin order issue. Xschem has a different pin order for standard cells putting the output Q or Y last where as the extracted netlist puts it third from last. The supply pins are jumbled as well. For example: --------------------------------------------------------------------------------------- Instance: sky130_fd_sc_hs__nand3_1_0 |Instance: sky130_fd_sc_hs__nand3_1:10 A = 6 | 1 = 6 B = 6 | 2 = 6 C = 6 | 3 = 6 VGND = 45 | 4 = 45 VPWR = 41 | 5 = 45 Y = 2 | 6 = 41 VNB = 45 | 7 = 41 VPB = 41 | 8 = 2 --------------------------------------------------------------------------------------- Has anyone else run into this? Any help would be appreciated.

Looks like xschem can’t find the standard cell libraries so they’re not getting netlisted and thus being compared as black boxes. In xschem, when you select the nand symbol and press

e

, do you descend into the nand schematic? Also your top level doesn’t have any ports. You want to have top level pins in the schematic and the corresponding pin layers and text in the top layout.

I can't descend into any of the standard cell schematics. I have added ports to the layout for clarity now. Are there .sch files for standard cells apart from symbols that I should have somewhere? I will try to find them and include them.

xschem does not use schematics for standard cells, as the functionality is provided by .spice files. For simulation this file is included which contains all standard cell netlists (this one for high density(hd) lib):

.include /home/schippes/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice

(of course your actual path depends on your open_pdks installation) Taking for example a NAND2_1 gate this is the port order as netlisted by xschem:

x1 A B VSS VSS VCC VCC IX sky130_fd_sc_hd__nand2_1

so inputs first, then power/body rails and output last. This matches the nand2 netlist found in above file:

.subckt sky130_fd_sc_hd__nand2_1 A B VGND VNB VPB VPWR Y
X0 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X1 VPWR B Y VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X2 VGND B a_113_47# VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X3 a_113_47# A Y VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u 
.ends

I manually added the

sky130_fd_sc_hs.spice

file in the produced netlist and it seems to work now. It does break the cells into their transistors now. Thank you.