Hello @Weston Braun, did you observe high switching current peaks in your simulations and/or measurements through your input source in your openPMIC design? what were your design considerations in this case? We get spikes up to ~1A with 2ns width between one of the state changes, but we are not sure if its a simulation artifact due to the fact that we use huge transistors without modeling the waffle parasitics (we are using your switches) or if they will atually be an issue in our design. If the second is the case, we would like to know how to take design actions, any advice?

When you switch you have a current due to I = C * dv/dt, with the drain and gate capacitance. I think I saw some current spikes? Are you sure you are not getting shoot through between the two parts though?

Thanks for the reply. What do you mean by "two parts"? And which bonding wire do you mean here, the one at the input supply voltage?

Are you using a PMOS high side switch and a NMOS low side switch? Are you driving them with the gates tied together or do they each have their own gate drive with deadtime between them?

We use flying cap topology, so 2 high side Pmos and 2 low side nmos, each of them with independent gate driver and dead Time We have experimented with dead time so that's not the issue

Well its likely just the charging / discharging of the drain source capacitances then