Hello All, We are trying to do the precheck of our...
# shuttle-precheck
j
Hello All, We are trying to do the precheck of our DCDC analog chipathon design through the Efabless platform but found some issues. Firstly, our GDS is quite big, around 250MB, so Github is complaining about the size. We compressed the file as "user_analog_project_wrapper.gds.gz" to have 43MB, and then did Git Pull in the Efabless platform. After that, we run the preckeck and it took long time before the job was stopped by the administrator (see screenshot below). I'm wondering which of the steps is the problem, could anyone here guide us? cc @Tim Edwards
t
We would have to look a the logs. @jeffdi might be able to give you an indication of why the job was killed (either a standard time-out, or out-of-memory error, or something else).
m
@Jorge Marin Has your design been flattened? Previously, some analog designs have been unnecessarily flatten resulting in large files. (Parasitic extraction requires flattening, but you don’t want to submit the flattened design.)
j
@Alfonso Cortés told me the design is not flattened @Tim Edwards how can we check the log files?
Hello @Tim Edwards @jeffdi, this is the project in which we find trouble, we would really appreciate if you could take a look: https://platform.efabless.com/projects/1427
@Mitch Bailey apparently part of the design is flattened, we use huge power transistors that have been generated using a tcl script. Do you have any workarounds in mind?
m
Can you identify repeating patterns in the waffles, create cells for those, and then place them as arrays?
👍 1
j
Ok, we'll try to do so