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Hi <@U016EM8L91B> <@U017X0NM2E7> I am failing the ...
# shuttle-precheck
t
Hi @User @User I am failing the consistency check: Layout check where the user project gds doesn't match the structural netlist (missing module is puf_top.v). I edited the verilog/rtl/user_analog_project_wrapper.v to include the puf_top.v module which is defined in design.lvs.v which has the flat structural netlist after synthesis. I am not sure exactly what this check is doing, for example, is it checking lvs against this user_analog_project_wrapper.v netlist? Thank you so much for your help. Here is my repo: https://github.com/lsammarone/OpenPUF Thread in #magic
@jeffdi: What does the check do that produces the message "*The GDS layout for user_analog_project_wrapper doesn't match the provided structural netlist*"? This project has a structural verilog netlist for 
user_analog_project_wrapper.v
that contains one instance of 
puf_top
. The GDS top cell 
user_analog_project_wrapper
also has one instance of 
puf_top
. What is the check looking for that isn't being satisfied?
@Luke Sammarone: Try removing 
xschem/user_analog_project_wrapper.spice
. It still represents the original example layout, and might be picked up preferentially over the verilog netlist, as it is also technically a top-level structural netlist.
l
@Tim Edwards thank you Tim and Jeff, removing user_analog_project_wrapper.spice didn't fix the issue.
@Tim Edwards @jeffdi when I flatten my top level user_analog_project_wrapper magic file before writing to gds, i pass this consistency check, but fail a bunch of klayout drc errors. I want to run through this again to see if the drc errors go away because I was passing when the layout was hierarchical
@Tim Edwards Hi Tim, I submitted my designed to efabless and precheck passes except for this layout consistency check. Do I need to fix this or is it okay? When I flatten the layout, I pass this check by fail DRC. I think this is because my design has standard cells and when flattened, they fail DRC. Please let me know what you think I should do, thank you!
t
@jeffdi: I approve this layout but I don't have the foggiest idea why precheck is flagging this "consistency check", or why it it flags "puf_top". There is a corresponding verilog file with the same hierarchical structure, so the error message doesn't make any sense.
l
@Tim Edwards OK thank you Tim! In this case, will we be able to tape out this gds? Just wanted to check because the 'tapeout' button is still grayed out since we aren't passing precheck 100%
t
@Luke Sammarone: I'm trying to get you to tapeout. . .
l
Thank you Tim 🙏
@Tim Edwards Hi Tim, I fixed the consistency error by extracting the netlist from the layout and putting it in netgen/user_analog_project_wrapper.spice
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