Are there any open-source 10 bit ADC for the sky130 technology?

search for "ADC" in https://platform.efabless.com/projects/public

Thanks!

Christoph Weiser has submitted variations on a 10 bit ADC for several shuttles, for example

Yes that is right. You find my contribution with a 10b SAR-ADC here. https://github.com/chrische-xx/mpw6

@Christoph Weiser: Do you really believe that you can get 10 bits out of an SAR design?

@Tim Edwards No of course not. This ADC has 10 bits of resolution. The effective number bits (ENOB) will always be lower due to the non-idealities in the system. But if the question was if a SAR-ADC in general could archive this in sky130: We don't have any mismatch information available, so its impossible to say. The SAR-ADC is fundamentally limited by how accurate unit elements match.

@Christoph Weiser do you have a gds file of only the SAR-ADC?

@Tiago Silva You can find a hierachical gds called design.gds.gz in the project repo. Using klayout you can save the sar_10b cell to a standalone gds file.

Got it, thank you very much!

@Christoph Weiser: Great! I also have an ADC design (now I wish I had made it 10 bits resolution on the same principle, but I left it at 8 bits. We (Efabless) needed one for a customer project. If I had known about yours I would have just adopted it. I think we only looked at what was available through MPW-five.

@Christoph Weiser sorry to bother again, but do you have a LEF file for the SAR-ADC? Or can I generate one with what you have in your repo? I'm still a newbie when it comes to this stuff, thanks again for the help.

@Tiago Silva: No Problem I'm glad to help. Unfortunately in this case I do not have a solution on hand though. What is your requirement for that LEF file? Is it because you need the pin locations of the layout for some automatic routing?

I'm trying to join my digital design with your ADC in caravel. The way I found to do it is to use both as macros and instantiate them in the user_project_wrapper in verilog. However, for that it needs the LEF files too. Is there another way to join the designs that doesn't require the LEF?

@Tiago Silva: Read the GDS into magic with the

gds read <file>

command, and write LEF with the

lef write -hide

command.

@Tim Edwards

% gds read sar_10b.gds

Don't know how to read GDS-II:

Nothing in "cifinput" section of tech file.

Probably yes because it works for me, Tim can confirm this. But in any case i noticed you will face another issue. I placed the text with the name of the pin on the labels layer (*/5) not on the pin layer (*/16). So if you don't move the text on the labels layers to the corresponding pin layers, the LEF will be empty.

@Tiago Silva: You need to have the open_pdks installation of skywater-pdk and start magic with, e.g.,

magic -d OGL -rcfile /usr/local/share/pdk/sky130A/libs.tech/magic/sky130A.magicrc

.

I'm getting the following errors when trying to run magic now:

I think your version of magic is too old.

The version was indeed too old. I got everything to work now and after all the steps you two described successfully outputted the LEF file. However, when I opened the gds in magic it gave me 4 DRC errors. Is that normal/ok?

@Tiago Silva: Its ok, the drc errors arise because its a hierachical gds you are running drc on. If you flatten the gds first you will see there are none.

I'm getting the following warnings that lead to an error when making the user_project_wrapper:

Warning: No pins in the LEF view of sar_10b0  marked for use as power

Warning: Attempting to match power pin by name (using top-level port name) for cell: sar_10b0

Warning: No pins in the LEF view of sar_10b0  marked for use as ground

Warning: Attempting to match ground pin by name (using top-level port name) for cell: sar_10b0

Warning: not all power pins found for cell: sar_10b0

Do you happen to have any idea on how to fix this? The LEF includes the power pins like this:

PIN avdd

PORT

LAYER met5 ;

RECT 515.180 21.840 527.820 28.240 ;

END

PORT

LAYER met5 ;

RECT 515.180 134.590 527.820 140.990 ;

END

END avdd

PIN avss

PORT

LAYER met5 ;

RECT 521.670 0.000 527.820 6.400 ;

END

PORT

LAYER met5 ;

RECT 521.670 156.430 527.820 162.830 ;

END

END avss

PIN dvdd

PORT

LAYER met5 ;

RECT 0.000 21.840 101.810 28.240 ;

END

PORT

LAYER met5 ;

RECT 0.000 134.590 101.810 140.990 ;

END

END dvdd

PIN dvss

PORT

LAYER met5 ;

RECT 0.000 0.000 3.890 6.400 ;

END

PORT

LAYER met5 ;

RECT 0.000 156.430 3.890 162.830 ;

END

END dvss

@Tiago Silva Are you able to integrate @Christoph Weiser ADC into your project ? Are you using openlane flow to integrate the IP ? As my understanding MPW-6/MPW-7 PDN does not handle macro which uses met-5 inside.

@Dinesh A No, in the end I couldn't do it and ended up submitting only my design. I'll try again for mpw7, but right now I have no idea where to begin. Sorry I couldn't help.