I am going through my initial results in character...
# analog-design
w
I am going through my initial results in characterizing the OTA I taped out on my IC and I am getting a simulated gain of 54dB but I am measuring a gain of 43dB on the bench. I am trying to make sense of this measurement. Is this at all to be expected for fabricated ICs? Thats a factor of ~3.5.
Its a cascode OTA, so the DC gain is dependent on the transconductance and output resistance.
r
Is this DC gain?
w
Yah.
ro should be dependent on lambda and Id, while gm is dependent on the square root of Id. I have no true way of checking as it goes through a few current mirrors, but my current should not be off by that much
r
Did you account for parasitic resistances?
Is Id at what you simulated it to be?
w
Oh, derp. This is the OTA used in the feedback loop of my DC/DC converter. I added two diode connected NMOS as an output clamp to limit the maximum compensator voltage and thus output current
I added that in the simulation and my simulated gain is now 46dB vs 43dB measured. And I suspect that is going to be rather sensitive to the DC output level.
l
You can use a buffer CMOS to measure it, so you can be sure that it is not the probe impedance is messing with your results. Try to simulate it with a 1 MOhm resistive load to see what happens.
w
I actually have it matching with sim within less than 1dB of gain now. I lowered the output voltage level so the clamp NMOS does not conduct
I am modeling the resistance of the feedback resistor and the probe. The output resistance of the amplifier is only ~300k though, so its pretty small compared to the 10M scope probe
I am limited by the capacitance of the test pad and the ESD protection resistor in series with the output but I am also able to verify that the 2nd pole is in excess of 70MHz if I use my VNA, which is pretty cool.
l
70 MHz is pretty good. And 300 kOhm isn't that small compared to a 10 MOhm load, if you want to match a simulation with infinite resistive impedance.