Hi, has anyone had issues with exporting the reram...
# reram
a
Hi, has anyone had issues with exporting the reram cells to GDS with magic? Here when we try to read the GDS back in (on the right) — it doesn’t match up the cell we started with (on the left). And we see DRC errors that weren’t there in the mag cell. Going by the docs we are only adding the ReRAM layer as a “via+oxide” in between M1 and M2. But the GDS doesn’t seem to capture the oxides. https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram/blob/48c8310e464157d797c78cb2e6d6b5a21d710c20/docs/user_guide.rst cc: @User @User
t
I see the error and will fix it. However, I think you should reduce the size of your ReRAM area until it fits only one contact cut. While the rule set says nothing about the possibility of multiple ReRAM devices connected on the same net, my guess is that the intention is one device only. The error is that the recipe for generating the via over/under the ReRAM is misaligning the via and the ReRAM layer. This misalignment would only show up when there is more than one ReRAM device in the drawn area.
👍 1
🙌 1
s
I am still facing some issues with exporting reram cells to GDS. When I try reading GDS back in (right), the reram layer (brown in left image) is imported as a via1 layer (pink in right image). @User @User
t
@User: I can reproduce the problem and I'm looking into it now.
@User: I just pushed a fix for the ReRAM GDS output and input in open_pdks on opencircuitdesign.com. I had some confusion over what is represented by the "reram_cell" layer, and what size it should be. According to the documentation, it seems that there is a minimum size but no maximum or fixed size, which I find a bit odd; I would think that a large ReRAM layer area could behave quite differently from a minimum-size ReRAM layer, not to mention something like a long ReRAM layer with multiple contacts. Anyway, the correction I just posted makes more sense to me, and it also reads back the same thing that it wrote out.