I was hoping to get some help in the next meeting regarding the open galaxy toolkit which I am working on through caravel user project. 1. In the "how tos" tutorial when they simulated their schematic design they did it by using ngspice but It happens that I do not have the ngspice tech file in open galaxy workspace instead it's showing spicepartsS3 and it does not have the "AnalysisProcessCorners.ic. " So my error is showing something like this in the figure @User helped me out and was kind enough to look through the workspace but the xschem was crashing and there were no tutorial on how to use the tools within VM. If anyone can help or can give me a good idea then that would be great!

One of the Efabless people should be able to help. @mkk @jeffdi @Tim Edwards

@Omiya Hassan: It looks like you're using Electric for schematic entry. We do not have support in Electric for the SkyWater process, only xschem. We have not yet reworked the efabless open galaxy project manager to include one-button-push launching of xschem, so you'll have to do that by running xschem from a terminal window. As you noted, xschem was crashing, but that was reported to us by Luis a few days ago, and we got it fixed, so you should be able to use it now on the platform.

thank you, i'll try it out and let you know

You must save in another place, not directly in this folder.

yup did it and it got saved successfully. thanks! Now I'm trying to simulate a 2input nand gate using ngspice

Remember to load the model files. Have you tried to simulate the examples?

loading the model files as in? and yes I am simulating an example and it's showing this. is it due to me not loading the model files?

I don't know much about digital simulation in xschem and ngspice. I guess it simulates the logic gates in the transistor level.

yup got access to it. I'll run an example and let you know if I face further issues.

Well, I've just tried the examples. They don't work, because the path to the transistor models aren't working.

ahh. So i guess I'll build one from the ground and try it out

My apologies. The links to the files are somehow screwed up on the efabless install; this is probably an error in the open_pdks Makefile. I'm looking into a fix, plus checking if there is a workaround you can use for now.

thanks so much. I'll wait for your update

It looks like the PDK has been incorrectly installed on the efabless server. There does not seem to be a simple workaround for it. I'll see how fast I can get it fixed.

Thanks Tim. highly appreciated

I didn't get a response from the platform maintainer yesterday, so we've now upped the issue to "urgent" status. I'll let you know when it has been taken care of.

thanks!

I'm sorry about the delay. The simple problem of the path to the ngspice models from the xschem symbols was fixed easily. However, simulation of the sky130 models in ngspice appears to require an update of ngspice on the platform. That's more complicated than just pulling the latest version of ngspice and compiling. It was promised to be done by today, but I will need to check the status.

thanks! and no worries, I was also on my day off due to labor holiday

Well, it hasn't been updated yet, and I will continue to push for completion.

could you guys tell me which software does open galaxy use to write verilog code and testbenches for digital hardware design and how to access them? thanks

In the past we have used

cloud-v

, which is not on Open Galaxy specifically (it is a cloud-based service), but generates output in a filesystem that can be accessed from Open Galaxy. CloudV was made by the same group that is developing OpenLane, so you might want to ask them what they recommend.

thanks, by the help of Dr. Murmann I was able to access cloudV and follow all the instructors documented in https://info.efabless.com/knowledgebase/the-efabless-digital-synthesis-flow/ The synthesizing is showing an error in "cannot include spi_slave.v" and I'm not sure how to fix it. Any idea? Also is there any tutorial similar to how to design an inverter using Magic for how to write verilog code for any simple design verification? Thanks