Perhaps @User can help...

@User @User @User. So we finished our mpw-precheck and tapeout and both succeeded. Could you guide us on the next steps that needs to be taken for final submission? our project (@User): https://efabless.com/projects/473

@User Chip 6 also is ready. mpw-precheck and tapeout both are succeeded. Submitter Confirmed is done Our project: https://efabless.com/projects/540

We couldn't finish the integration of our three projects at top level at all. Anyway, I tried to submit my project to efabless and it didn't work at all. A precheck of an incomplete version of our chip (Chip 3 - https://efabless.com/projects/476 ) failed... I'm using analog only blocks and no schematics at all. All blocks were directly designed at layout level using Magic, extracted and simulated using ngspice. There are no top netlists for XOR checks, nor LVS checks, as there are no xschem files at all. There are no verilog files as there are no digital cells. It fails some KLayout checks, although it passes all Magic DRC checks. The individual blocks are ok. How can I fix it?

[11/28/21 15:20:48 PST] SUBMITTED

            [11/28/21 15:25:13 PST] STARTED


            [11/28/21 15:25:15 PST] PROJECT GIT INFO
            Repository: <https://github.com/lhrodovalho/sscs-pico-afe-vco-vga.git> | Branch: main | Commit: 866a205d22fcebe62ab8fcb0774d23921f9099c0

            [11/28/21 15:25:15 PST] EXTRACTING GDS
            Extracting GDS files in: sscs_pico_chip_3

            [11/28/21 15:25:15 PST] PROJECT GDS INFO
            user_analog_project_wrapper: e63c6af88eb0653c61f739160e576601304fedf0

            [11/28/21 15:25:15 PST] TOOLS INFO
            KLayout: v0.27.3 | Magic: v8.3.220

            [11/28/21 15:25:15 PST] PDKS INFO
            Open PDKs: 14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb

            [11/28/21 15:25:15 PST] START
            Precheck Started, the full log 'precheck.log' will be located in 'sscs_pico_chip_3/jobs/mpw_precheck/872ee74e-f428-400a-be9f-3ece5190f93f/logs'

            [11/28/21 15:25:15 PST] PRECHECK SEQUENCE
            Precheck will run the following checks: Manifest Makefile Consistency XOR Magic DRC Klayout FEOL Klayout BEOL Klayout Offgrid Klayout Metal Minimum Clear Area Density Klayout Pin Label Purposes Overlapping Drawing Klayout ZeroArea

            [11/28/21 15:25:15 PST] STEP UPDATE
            Executing Check 1 of 11: Manifest

            [11/28/21 15:25:15 PST] MANIFEST CHECKS FAILED
            Manifest checks failed. Caravel version does not match. Please rebase your Repository to the latest Caravel master.

            [11/28/21 15:25:15 PST] STEP UPDATE
            Executing Check 2 of 11: Makefile

            [11/28/21 15:25:16 PST] MAKEFILE CHECK PASSED
            Makefile valid.

            [11/28/21 15:25:16 PST] STEP UPDATE
            Executing Check 3 of 11: Consistency

            [11/28/21 15:25:16 PST] CONSISTENCY CHECK FAILED
            caravan.spice file was not found.

            [11/28/21 15:25:16 PST] CONSISTENCY CHECK FAILED
            The user netlist and the top netlist are not valid.

            [11/28/21 15:25:16 PST] STEP UPDATE
            Executing Check 4 of 11: XOR

            [11/28/21 15:25:19 PST] XOR CHECK FAILED
            The GDS file has non-conforming geometries.

            [11/28/21 15:25:20 PST] STEP UPDATE
            Executing Check 5 of 11: Magic DRC


            [11/28/21 15:25:23 PST] MAGIC DRC CHECK PASSED
            The GDS file, user_analog_project_wrapper.gds, has no DRC violations.

            [11/28/21 15:25:23 PST] STEP UPDATE
            Executing Check 6 of 11: Klayout FEOL

            [11/28/21 15:25:25 PST] KLAYOUT FEOL CHECK FAILED
            The GDS file, user_analog_project_wrapper.gds, has DRC violations.

            [11/28/21 15:25:26 PST] STEP UPDATE
            Executing Check 7 of 11: Klayout BEOL

            [11/28/21 15:25:42 PST] KLAYOUT BEOL CHECK PASSED
            The GDS file, user_analog_project_wrapper.gds, has no DRC violations.

            [11/28/21 15:25:42 PST] STEP UPDATE
            Executing Check 8 of 11: Klayout Offgrid

            [11/28/21 15:25:46 PST] KLAYOUT OFFGRID CHECK PASSED
            The GDS file, user_analog_project_wrapper.gds, has no DRC violations.

            [11/28/21 15:25:46 PST] STEP UPDATE
            Executing Check 9 of 11: Klayout Metal Minimum Clear Area Density

            [11/28/21 15:25:47 PST] KLAYOUT METAL MINIMUM CLEAR AREA DENSITY CHECK PASSED
            The GDS file, user_analog_project_wrapper.gds, has no DRC violations.

            [11/28/21 15:25:47 PST] STEP UPDATE
            Executing Check 10 of 11: Klayout Pin Label Purposes Overlapping Drawing

            [11/28/21 15:25:49 PST] KLAYOUT PIN LABEL PURPOSES OVERLAPPING DRAWING CHECK PASSED
            The GDS file, user_analog_project_wrapper.gds, has no DRC violations.

            [11/28/21 15:25:49 PST] STEP UPDATE
            Executing Check 11 of 11: Klayout ZeroArea

            [11/28/21 15:25:50 PST] KLAYOUT ZEROAREA CHECK PASSED
            The GDS file, user_analog_project_wrapper.gds, has no DRC violations.

            [11/28/21 15:25:50 PST] FINISH
            Executing Finished, the full log 'precheck.log' can be found in 'sscs_pico_chip_3/jobs/mpw_precheck/872ee74e-f428-400a-be9f-3ece5190f93f/logs'

            [11/28/21 15:25:50 PST] FAILURE
            4 Check(s) Failed: ['Manifest', 'Consistency', 'XOR', 'Klayout FEOL'] !!!

            [11/28/21 15:25:50 PST] FAILED

Hello everyone! , We have successfully completed submission of Chip#2 . Thanks everyone for providing support throughout the process. Special thanks to @User @User @User @User.

image.png

@User hello. i’m reviewing your project and precheck results.

Looks like there are a few issues that need to be resolved: 1. project directory and manifest check 2. netlist check 3. XOR check 4. front-end DRC errors (reported by klayout)

for the first couple of items, could you please do a ‘Git Pull’ from the Workspace tab on the Project Details View? Looks like you are missing the caravel directory under the project root. Please add that to your repo.

you will also need to provide spice netlist for caravan (caravan.spice).

@User hi jeff, since there are two teams USA and EGYPT @User, for delivery purposes do we sign and attach two compliance forms in the same activity tab before submission? and do we give two shipping addresses in our submission tab? Our design is complete

Hi All, Is it possible to share with me the devices you have used in your projects (especially analog). We are trying to compile all devices that are relevant so that we could improve their spice models. Please try to fill in the doc and add comments if needed. https://docs.google.com/spreadsheets/d/1kLTIA6ApmF_jT6hFPHfaQRv56rYEccMIJppA5aw7YW0/edit#gid=0

Hello everyone. Is there a better way to get the design layouts images than just take a screenshot?

Is there a way to get access to the full chip GDS after the full caravel tapeout process?

Does anybody know the latest on the tapeout status from the end of November tapeout? mpw-3/2110c?

@User any update on the delivery date?

expected fabout for the wafers is mid May. They will be some time for packaging and assembly after that.

@User has left the channel

We're designing a pcb to interface with the WCSP chips we get back (we have an analog design and the dev boards won't meet all of our needs interfacing with the design), does anybody have any experience mounting WCSP chips? I would assume it's similar to baking a QFN (minus solder paste), but I'm concerned about alignment since the solder ball pitch is only about .5mm Not sure if this can be done by hand or if it requires some pick and place. Thanks.

Hello @jeffdi, would You be so kind and provide any update on the delivery date ?

@Krzysztof Herman sorry - which shuttle?

@jeffdi we have participated in SSCS Pico 2021 program however our design was submitted as MPW-3

Wafers for mpw3 are being bumped. Will complete in August.

@jeffdi Thank You, looking forward to give it a try!

@jeffdi any update on the MPW3 chip delivery (SSCS Pico design contest submission)? The latest update was that it’s scheduled to be completed by August.

@Laura Chan has left the channel

@Luca Buonanno has left the channel

Hi guys ! Is there a vacancy in any team for the upcoming SSCS PICO Chipathon?

@Emmanuel Innocent has left the channel

@Tayyeb Mahmood has left the channel