<@U01RSNFAM55> first of all thank You Boris for th...
# ieee-sscs-dc-21q3k
Krzysztof Herman
09/09/2021, 11:58 AM@User first of all thank You Boris for this initiative and encouraging us to participate more in the discussions, we appreciate that. In fact would be fantastic to have some support in the field of the chip area optimization and routing strategies. We have performed a first approximation of our core area and now we are trying to optimize it in order to replicate it as many times as possible. The design passes the digital flow however, when we limit the user project area the router get into problems. Would be great if You could contact us with some experts in the field, who could give us a hint. Kind regards.
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Boris Murmann
09/09/2021, 2:05 PMHi Kzysztof, are you using OpenLane? Let's see if @mehdi can provide some pointers for your problem.
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mehdi
09/09/2021, 2:10 PMHi @Krzysztof Herman I can try to help you with that. Can you share a github link to your testcase and a description of your issue. I ll try to take a look today
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Krzysztof Herman
09/10/2021, 12:33 AMHi @Boris Murmann and @mehdi. Yes I am using open lane, This is the repository I am working on. https://github.com/KHermanUBB/caravelSonarOnChip.
Krzysztof Herman
09/10/2021, 12:34 AMI was ale to get a gds of one channel as a macro "user_proj_example" and it looks as follows
Krzysztof Herman
09/10/2021, 12:35 AMSonarOnChip.xor.gds.png
Krzysztof Herman
09/10/2021, 12:37 AMIn general I had some problems with routing, I mean, in order to complete the routing without errors I had to use "routeability driven placement"
Krzysztof Herman
09/10/2021, 12:39 AMwould be great if You could recommend some routing strategies in order to setup the flow with correct parameter values
Krzysztof Herman
09/10/2021, 1:04 AMOur design pretends to replicate one module until exhausta all 38 IO. I did one experiment slicing the mprj area into 10 strips and have tried to use the area of one strip. I was able to pass through the flow only when I had allowed the congestion.
Krzysztof Herman
09/10/2021, 1:05 AMSonarOnChip.def.png
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mehdi
09/10/2021, 1:20 AMAre you planning to have 38 tiles of what you have on the bottom left?
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Krzysztof Herman
09/10/2021, 1:30 AMthis is the maximum we would like to have
Krzysztof Herman
09/10/2021, 1:31 AMin general we do not have problems with timing because our design is relatively slow
Krzysztof Herman
09/10/2021, 1:33 AMwhat costs is the routing, seems that there is a lot of congestion even if the PL_TARGET_DENSITY was set to 0.3
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mehdi
09/10/2021, 1:37 AMI think it would make sense to discuss this over zoom. Making 38 tiles might be a solution but then you need to make sure pin connections are adequately positioned for the routing at the top. I can probably meet tomorrow afternoon EST time? email: mehdi@umich.edu
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Krzysztof Herman
09/10/2021, 1:39 AMtomorrow afternoon I am complicated, in the morning could be
Krzysztof Herman
09/10/2021, 1:40 AMor other day, monday o tuesday
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mehdi
09/10/2021, 1:41 AMOk, Moday afternoon should work for me as well
k
Krzysztof Herman
09/10/2021, 1:42 AMperfect
Krzysztof Herman
09/10/2021, 1:43 AMI will contact You Monday's afternoon
Krzysztof Herman
09/10/2021, 1:43 AMThanks a lot!
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mehdi
09/10/2021, 1:43 AMplease send an invite 🙂 (email is above)
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Krzysztof Herman
09/10/2021, 1:44 AMok, I will